Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1998-08-27
2001-04-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S167000, C438S570000, C257S260000, C257S280000, C257S281000
Reexamination Certificate
active
06218222
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device with a rectifying Schottky junction, comprising a semiconductor body with a semiconductor substrate, by which method a stack is formed in the semiconductor body of a first semiconductor region of a first conductivity type formed by means of epitaxy and a second semiconductor region having a small thickness and a high doping concentration, and by which method a metal layer is provided on the semiconductor body at the area of the second semiconductor region so as to form the Schottky junction with the semiconductor body, and the thickness and doping concentration of the second semiconductor region are chosen such that the height of the Schottky barrier of the Schottky junction is influenced, while a third semiconductor region of a second conductivity type opposed to the first is provided from the surface of the semiconductor body into the first semiconductor region at at least two mutually opposed sides of the second semiconductor region.
Such a method is used for giving a Schottky barrier, wherever this is used, a current-voltage characteristic, especially in the forward direction, which is most suitable for the application. The use of a thin, strongly doped barrier layer renders possible a greater variation in said characteristic than is possible, for example, through the choice of different Schottky metals.
Such a method is known from U.S. Pat. No. 4,089,020. It is described therein (see
FIG. 4
) how a first n-type semiconductor region is formed as an epitaxial layer on an n-type silicon semiconductor substrate. In the semiconductor region thus formed, a thin, strongly doped second semiconductor region of p-type silicon is formed by means of implantation, acting as a layer which influences the barrier for a Schottky junction to be formed. This junction is provided with an annular third semiconductor region which embraces the second semiconductor region at at least two mutually opposed sides, entirely surrounding it in this case, which third region is formed from the surface of the semiconductor body through the local diffusion into it of p-type impurities and is provided with a doping concentration and a geometry such that leakage currents and breakdown at the edge of the Schottky junction to be formed are limited and prevented, respectively, acting as a so-called guard ring. A metal layer of aluminum, which forms a Schottky junction with the semiconductor body, is provided on the surface of the semiconductor body and in contact with the second semiconductor region. The substrate is provided with an ohmic contact.
A disadvantage of this method is that the properties of the devices obtained thereby, in particular the current-voltage characteristic, are not satisfactorily controllable and in addition not well reproducible. The known method is less suitable for mass manufacture on account of this.
SUMMARY OF THE INVENTION
It is an object of the invention to counteract said disadvantage and to provide a method which yields devices with well controllable and reproducible properties.
According to the invention, a method of the kind mentioned in the opening paragraph is for this purpose characterized in that the second semiconductor region is formed by means of low-temperature gas phase epitaxy and is given the first or second conductivity type, in that the third semiconductor region is formed by means of ion implantation, and in that the second semiconductor region is formed after the third semiconductor region has been formed. The invention is based on the surprising recognition that ion implantation is not the most suitable technique for forming the second semiconductor region, in particular if this region is very thin and strongly doped. A very low implantation energy is necessary for forming this region then, for example 5 to 15 keV. Such a low implantation energy is difficult to adjust and to reproduce. In addition, the use of ion implantation requires a subsequent heat treatment for activating the implantated ions electrically. It is necessary for this to bring the semiconductor body to, for example, 900° C. during 20 minutes. This is found to lead to an unacceptably great and badly controllable diffusion of the implanted ions, especially if a high doping concentration or a small thickness is chosen for the second semiconductor region, in particular when phosphorus ions are implanted. The invention is also based on the recognition that gas phase epitaxy is a more suitable alternative in these respects. This process can be carried out very well already at, for example, 700° C., and the growing time required for very thin layers—also at the comparatively low growing rates which accompany such a low growing temperature—is still limited to, for example, one to ten minutes (inclusive of heating-up and cooling-down). The fact that the third semiconductor region is formed by means of ion implantation instead of diffusion also reduces the thermal treatment of the semiconductor body required for the formation of this region. This benefits the sharpness of the interface between the epitaxial layer and the substrate.
Since ion implantation still leads to an unacceptable thermal load on the second semiconductor region, as was discussed above, the gas phase epitaxy for forming the second semiconductor region is not carried out until after the third semiconductor region has been formed by means of implantation in the method according to the invention. This is also surprising because in general a diffusion and an implantation (including annealing) are carried out after any gas phase epitaxy. The invention is also partly based on the recognition and the experimental confirmation thereof that the consequence of the above, i.e. that the second semiconductor region lies above the third semiconductor region, does not have any negative consequences for a good operation of the obtained device. This holds irrespective of the conductivity type of the second semiconductor region, which may be equal to or opposed to that of the third semiconductor region. Thanks to this freedom, the barrier of the Schottky junction can be raised as well as lowered, which considerably widens the range over which the current-voltage characteristic can be varied. The devices obtained by the method according to the invention are found to have very well controllable and reproducible properties. As a result of this, and because the method according to the invention is simple, the latter is eminently suitable for mass manufacture of in particular discrete Schottky diodes.
In a first embodiment of a method according to the invention, after the third semiconductor region has been provided in the first semiconductor region, first the second semiconductor region is provided over the entire surface of the semiconductor body by means of non-selective gas phase epitaxy, and subsequently the metal layer is provided by means of non-selective deposition, whereupon the metal layer is removed from outside an edge which lies within the third semiconductor region, as seen in projection. Such a method has the important advantage that it comprises comparatively few steps. The metal layer may be provided in the same piece of equipment in which the second semiconductor region is formed. The devices obtained by this embodiment of the method have excellent properties. A silicon nitride layer may be provided over the surface, with a contact opening therein above the metal layer, by means of a plasma deposition technique for the purpose of passivating the device.
In an embodiment which is also very favourable, after the formation of the first and third semiconductor regions, the surface of the semiconductor body is provided with an electrically insulating layer which is subsequently provided with an opening whose edge, seen in projection, lies within the third semiconductor region, after which the second semiconductor region is provided in said opening by means of selective gas phase epitaxy, and finally the metal layer is deposited over the su
Brown Adam R.
De Boer Wiebe B.
Biren Steven R.
Lee Granvill
Smith Matthew
U.S. Philips Corporation
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