Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2001-03-27
2002-10-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C257S407000
Reexamination Certificate
active
06465290
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention directs to a method of manufacturing a semiconductor device, particularly, to a method of manufacturing a semiconductor device featured in the ion implantation step and to a method of manufacturing a semiconductor device featured in the step of forming the gate electrode of a transistor.
2. Description of the Related Art
In recent years, a large scale integration (“LSI”), in which many transistors and resistors are connected to each other to form an electric circuit and are mounted integrally on a single chip, could be used in some portions of an electronic computer or a communication appliance. Therefore, the performance of an entire apparatus can be heavily related to the performance of the LSI single body. The performance of the LSI single body can be improved by increasing the degree of integration, i.e., by improving the elements quality of the chips.
The elements can be improved by rendering optimum the ion implantation for forming the diffusion layers, such as the source-drain diffusion layers and the annealing treatment after the ion implantation. As a result, it is possible to obtain a metal oxide semiconductor (“MOS”) transistor having shallow source-drain diffusion layers having a depth not larger than 0.2 &mgr;m.
If ions are implanted into a silicon substrate, crystal defects can be generated in the silicon substrate. It is commonly known in the art that the crystal defects do not decrease in the subsequent heat treatment, thus causing the weakening of the mechanical strength of the silicon substrate by multiple repetitions of the ion implantation and the heat treatment process.
The silicon substrate may be cooled during the ion implantation process to avoid the problem discussed above, thereby suppressing the migration of the atomic void during the ion implantation. As a result, it is possible to permit the interstitial atom introduced by the ion implantation to be coupled with the atomic void so as to eliminate the defect.
However, if a silicon substrate is cooled to about −160° C. and an ion implantation is applied to the silicon substrate by masking the region other than the region in which the ion implantation is performed with a photoresist used in an ordinary lithography, cracks
122
are generated in a resist mask
118
, as shown in a cross sectional view in FIG.
1
. It is commonly understood that one of the causes of a crack may be attributable to the fact that water within the photoresist was initially frozen then when submitted to heat treatment, the volume of the water expands. If cracks are generated in the resist, ions are implanted into the masked region, too, so as to deteriorate the pn junction characteristics, resulting in failure to obtain a desired atomic characteristic. In the worst scenario, cracks can also be generated in the underlying insulating film where the cracks are generated on the resist pattern. The problem is that, if a crack is generated in the photoresist, ions are implanted into an undesired region. This phenomenon will now be explained with reference to FIG.
1
.
Specifically,
FIG. 1
is a cross sectional view of a construction of a Complementary Metal Oxide Semiconductor-Field Effect Transistor (“CMOS-FET”) where an ion implantation is performed using a conventional photoresist as a mask.
The CMOS-FET shown in
FIG. 1
is obtained by the following steps. In the first step, an n-type well
112
, a p-type well
113
, and an insulating film
114
for element isolation are formed in a semiconductor substrate
111
. Then, a gate insulating film
115
is formed on the surface of the semiconductor substrate
111
, followed by forming a gate or a dummy gate
116
, which will be described in further detail. After formation of electrode
116
, a p-type impurity layer
117
is formed by implanting ions of boron (“B”) or boron fluoride (“BF
3
”) into semiconductor substrate
111
in a concentration of approximately 1×10
14
to 5×10
15
cm
−2
. Further, a photoresist layer is formed in a thickness of approximately 0.5 to 1.5 &mgr;m, followed by applying a light exposure and development so as to obtain a photoresist pattern
118
. The photoresist pattern
118
thus formed is used as a mask for forming n-type impurity layers
120
.
In the next step, an n-type impurity
119
such as arsenic (“As”) or antimony (“Sb”) is implanted in a concentration of approximately 1×10
14
to 5×10
15
cm
−2
as shown in
FIG. 1
while cooling the substrate and having photoresist mask
118
formed thereon to temperatures not higher than −150° C. The method of manufacturing a transistor by using a photoresist mask as described has its shortcomings. Specifically, a crack
122
is generated in photoresist mask
118
in the cooling stage of semiconductor substrate
111
. Therefore, n-type impurity
119
passes through crack
122
to form an n-type diffusion layer
121
in p-type impurity layer
117
. As a result, the leak current through the pn junction is increased by at least two folds and, thus, it may not be possible to obtain good element characteristics.
Another method of miniaturizing the element may include using a dummy gate. In this method, a dummy gate of a laminate structure consisting of a silicon nitride film and a polycrystalline silicon (“poly-Si”) film is formed first, followed by forming source-drain regions and an interlayer insulating film. Then, the surface of the dummy gate is exposed and the dummy gate is removed, followed by newly formed metal gate film. A transistor comprising a gate film formed by this method is called a damascene gate Metal Oxide Semiconductor Field Effect Transistor (“MOSFET”). An example of a manufacturing method of a damascene gate MOSFET will be described below.
FIGS. 2A
to
2
C and
3
A to
3
C collectively show another method of manufacturing a transistor by using a dummy gate.
In a first step, the structure shown in
FIG. 2A
is prepared and can be obtained as follows. Specifically, a groove is formed by dry etching on the surface of a silicon semiconductor substrate
71
, followed by forming an insulating film within the groove by means of deposition or coating. It is possible to use a silicon oxide film as the insulating film. Alternatively, it is also possible to use a film of silicon nitric oxide (“SiNO”) having a thermal expansion coefficient close to that of silicon, i.e., about 3 ppm/K. The surface of the insulating film thus formed is polished by a chemical mechanical polishing (“CMP”) method or a mechanical polishing (“MP”) method so as to form an insulating film
72
for element isolation.
Then, an oxide film
73
for a dummy gate is formed by thermal oxidation in a thickness of about 3 to 10 nm on an element region surrounded by insulating film
72
for element isolation, followed by forming a film for a dummy gate on oxide film
73
. A laminate film consisting of a silicon nitride (“Si
3
N
4
”) film and an amorphous silicon film or a laminate film consisting of a silicon nitride film and a poly-Si film are used as the film for the dummy gate. The film for the dummy gate thus formed is subjected to an anisotropic etching so as to form a dummy gate
90
equal in shape to the gate. In
FIG. 2A
, dummy gate
90
comprises an amorphous silicon film or poly-Si film
90
a
and a Si
3
N
4
film
90
b.
The particular laminate structure makes it possible to prevent the surface of the poly-Si film from being exposed to the outside in the subsequent planarizing process. As a result, it is possible to prevent the poly-Si film from performing a silicidation reaction with cobalt (“Co”) in the subsequent silicidation process. Incidentally, the poly-Si film is selected as a material with a large etching selectivity relative to the thin insulating film
73
so as to permit the thin insulating film
73
to perform the function of the etching stopper in the step of removing the dummy gate, i.e., in the step of removing the poly-Si film, which is carried out after the silicidation process. It is
Matsuo Kouji
Murakoshi Atsushi
Niiyama Hiromi
Sato Yasuhiko
Suguro Kyoichi
Frommer & Lawrence & Haug LLP
Kabushiki Kaisha Toshiba
Nelms David
Pan Grace L.
Vu David
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