Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-07-28
2002-10-15
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S158000, C438S162000, C438S143000, C438S473000, C438S486000, C438S487000
Reexamination Certificate
active
06465288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device using a crystalline semiconductor film that is formed by crystallizing an amorphous semiconductor thin film. In particular, the invention relates to a manufacturing method of such semiconductor devices as a thin-film transistor (TFT).
2. Description of the Related Art
In recent years, techniques of constructing a semiconductor circuit by forming TFTs on a glass substrate or the like have advanced rapidly. A typical example of such semiconductor circuits is an electro-optical device such as an active matrix liquid crystal display device.
The active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and driver circuits are provided on the same substrate. Further, the system-on-panel device which additionally incorporates a memory circuit and logic circuits such as a clock generation circuit is being developed.
Since driver circuits and logic circuits are required to operate at high speed, it is not appropriate for those circuits to use an amorphous silicon film as an active layer. Therefore, TFTs using a crystalline silicon film (polysilicon film) as an active layer are now becoming the mainstream.
On the other hand, researches and developments are now being made on what is called a low-temperature process, that is, a process for forming a crystalline silicon film over a large area on such a substrate as a glass substrate that is low in heat resistance than a quartz substrate.
The present inventors disclosed a technique of forming a crystalline silicon film a glass substrate (see Japanese Patent Application Laid-open No. Hei. 7-130652). technique disclosed in this publication is such that a catalyst element for accelerating crystallization is added to an amorphous silicon film and then the amorphous silicon is crystallized by a heat treatment.
This crystallization technique has made it possible to reduce the crystallization temperature of an amorphous silicon film by as much as 50°-100° C. and to reduce the crystallization time to ⅕ to {fraction (1/10)} of the previous one. As a result, it has become possible to form a crystalline silicon film over a large area on a glass substrate that is low in heat resistance. It has been confirmed experimentally that a crystalline silicon film formed by such a low-temperature process has superior crystallinity.
In the above crystallization technique, metal elements such as nickel and cobalt are used as the catalyst element. Such a metal element forms deep energy levels in a silicon film and thereby captures carriers. Therefore, there is a possibility that the metal element adversely affects the electrical characteristics and the reliability of TFTs that are manufactured by using a crystalline silicon film containing the metal element.
It has been found that a catalyst element remaining in a crystalline semiconductor thin film segregates in an irregular manner, particular at grain boundaries. The inventors think that segregated regions serve as leak paths of faint current and possibly cause a sudden increase of an off-current (i.e., a current during an off-state of a TFT).
Therefore, it is desirable that the catalyst element be removed or reduced in concentration to such a level as not to influence the electrical characteristics at an early stage after the crystallization. The inventors have already filed an patent application that relates to a method of gettering a catalyst element in a crystalline silicon film by utilizing a gettering effect of a halogen element.
However, the this technique cannot be applied to a glass substrate that is low in heat resistance because a heat treatment needs to be performed at as high a temperature as 800° C. or more. Therefore, the features of the low-temperature process using a catalyst element cannot be used effectively.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems in the art, and an object of the invention is therefore to provide a technique for removing a catalyst element from a crystalline semiconductor film containing silicon or reducing its concentration therein while the features of the low-temperature process are maintained.
To attain the above object, the invention provides a manufacturing method of a semiconductor device which mainly comprises: 1) a step of crystallizing an amorphous semiconductor film comprising silicon by utilizing a catalyst element; 2) a step of forming a gettering region by selectively doping a crystallized semiconductor film with a group-13 element (specifically, boron) and a group-15 element (specifically, phosphorus); 3) a step of performing a heat treatment to move the catalyst element in a gettering subject region to the gettering region. With execution of the above steps, the catalyst element in the region that was not doped with the group-13 element nor the group-15 element is diffused into the gettering region and gettered there.
The basic object of the invention is to remove, from a crystalline silicon film, a catalyst that has been used to crystallize an amorphous semiconductor film containing silicon. To this end, a region in which a group-13 element and a group-15 element are introduced is used as a gettering sink.
In the above-mentioned crystallizing step, a catalyst element may be introduced into an amorphous silicon film by vapor-phase methods such as plasma doping, evaporation, and sputtering, or a method of applying a solution containing a catalyst element. In the method of using a solution, the amount of introduction of a catalyst element can be controlled easily and the catalyst element can easily be added at a very small amount.
Examples of the catalyst element are metal elements such as Ni (nickel), Co (cobalt), Fe (iron), Pd (palladium), Pt (platinum), Cu (copper), and Au (gold). Experiments of the inventors have revealed that nickel is the most suitable element.
In the invention, the group-13 impurity element for gettering is at least one element selected from B, Al, Ga, In, and Tl. B (boron) is the most suitable for this purpose. Examples of the group-15 impurity element are N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth). Phosphorus exhibits the most remarkable effect and arsenic is the second.
A technique is known in which an n-type region containing diffused phosphorus is used as a gettering sink for gettering a metal element that has diffused in a single crystal silicon substrate. In contrast, the invention has a feature that a region in which a group-13 element for imparting p-type conductivity to a semiconductor material as well as a group-15 element for imparting n-type conductivity to it is introduced is used as a gettering sink for gettering a catalyst element that has been added intentionally for crystallization.
REFERENCES:
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5648277 (1997-07-01), Zhang et al.
patent: 5675176 (1997-10-01), Ushiki
patent: 5700333 (1997-12-01), Yamazaki
patent: 5830784 (1998-11-01), Zhang
patent: 5874325 (1999-02-01), Koike
patent: 5932893 (1999-08-01), Miyanaga
patent: 5985740 (1999-11-01), Yamazaki
patent: 6074901 (2000-06-01), Ohtani
patent: 6087679 (2000-07-01), Yamazaki
patent: 6093587 (2000-07-01), Ohtani
patent: 6121660 (2000-09-01), Yamazaki
patent: 6140166 (2000-10-01), Ohtani
patent: 6140667 (2000-10-01), Yamazaki
patent: 6153445 (2000-11-01), Yamazaki et al.
patent: 6156628 (2000-12-01), Ohnuma et al.
patent: 6162704 (2000-12-01), Yamazaki et al.
patent: 6165824 (2000-12-01), Takano et al.
patent: 6197624 (2001-03-01), Yamazaki
patent: 6197626 (2001-03-01), Yamazaki et al.
patent: 7-130652 (1995-05-01), None
patent: 7-135318 (1995-05-01), None
Robinson Eric J.
Robinson Intellectual Property Law Office PC
Semiconductor Energy Laboratory Co,. Ltd.
Wilczewski Mary
LandOfFree
Method of manufacturing a semiconductor device using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2980069