Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-31
2003-02-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06518158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices with a fuse forming a redundancy circuit for repairing a defective product and a manufacturing method thereof.
2. Description of the Background Art
FIG. 8
shows an exemplary structure of a semiconductor device with three interconnection layers and a fuse. In this semiconductor device, on a surface of a silicon substrate
1
serving as a semiconductor substrate, a field oxide film
10
is selectively formed as an isolating insulating film. Further, a fuse
11
is selectively formed from polycrystalline silicon so as to contact with an upper side of field oxide film
10
. Fuse
11
is an element constituting a redundancy circuit for repairing a defective. Through the blow of fuse
11
by a laser, a defective portion can be disconnected and a normal portion can be employed instead, if necessary.
When fuse
11
of polycrystalline silicon is to be formed on a semiconductor device, which is a so-called “three-layer product”, having three interconnection layers on a semiconductor substrate with an insulating layer interposed between each interconnection layer and its adjacent layer, total thickness of three oxide films
21
a
,
21
b
,
21
c
serving as insulating layers for mutually isolating interconnection layers
23
a
,
23
b
,
23
c
exceeds 20,000 Å. Therefore, when the blow of the fuse is necessary to repair a defective product, for example, a significantly high output of the laser is required for blowing the fuse. When the output of the laser is extremely high, however, the radiation of laser causes a crack in the field oxide film under the fuse and the blown fuse directly contacts with silicon substrate
1
whereby a minute current flows.
To solve the problem described above, the oxide film can be thinned in a region above the fuse as shown in FIG.
9
. Such structure is described in Japanese Patent Laying-Open No. 9-51038, for example. With such structure, the fuse can be securely blown by the laser with an output of the same level both in the three-layer product and a product with one layer of an oxide film. At the same time, as the fuse blow is possible with a low laser output, undesirable effect such as crack of the field oxide film can be prevented.
Next, a process for obtaining the structure shown in
FIG. 9
will be described.
First, a structure shown in
FIG. 10
is formed. In particular, a field oxide film
10
with a thickness of about 5000 Å is formed on a silicon substrate
1
, and a fuse
11
of polycrystalline silicon is formed on field oxide film
10
. Then, an oxide film
21
a
with a thickness of about 8000 Å is formed so as to cover fuse
11
. A vertical interconnection
22
a
electrically connecting a contact
13
with an upper part is provided to form a first interconnection layer
23
a
. Then an oxide film
21
b
with a thickness of about 12,000 Å is formed so as to cover an upper side of first interconnection layer
23
a
. Then, a vertical interconnection
22
b
electrically connecting first interconnection layer
23
a
with an upper part is provided to form a second interconnection layer
23
b
. Further, a vertical interconnection
22
c
electrically connecting second interconnection layer
23
b
with an upper part is provided to form a third interconnection layer
23
c
. Thus the structure shown in
FIG. 10
is obtained.
With reference to
FIG. 11
a photolithography is performed to form a resist mask
14
for removing oxide film
21
c
in a region including a region
26
(hereinafter referred to as “fuse region”) above fuse
11
by the etching. Here, resist mask
14
is formed with an opening slightly wider than fuse region
26
therein to accommodate the decrease in the opening area in a subsequent step caused by the formation of a glass coat
12
(see
FIG. 9
) with a thickness.
With reference to
FIG. 12
, oxide film
21
c
with the thickness of about 8000 Å is removed by the wet etching and dry etching using resist mask
14
. After the removal of resist mask
14
, glass coat
12
is deposited through CVD (Chemical Vapor Deposition). Further, a mask (not shown) is formed on glass coat
12
for the formation of the opening in glass coat
12
. Then the photolithography and etching are performed so as to form fuse region
26
with a predetermined opening pattern. Then with the removal of the material of mask, the structure shown in
FIG. 9
is eventually obtained.
When the structure as shown in
FIG. 9
as described above is to be obtained, in order to form an opening in fuse region
26
, an additional mask must be formed after the formation of glass coat
12
, and then the photolithography and the etching must be formed. Thus the number of the required process steps increases. In addition, an additional amount of the mask material is necessary.
Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof allowing the reduction in the number of process steps and the amount of necessary mask material.
SUMMARY OF THE INVENTION
To solve the problems described above, a method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a fuse in contact with an upper surface of the isolating insulating film formed on a main surface of a semiconductor substrate; forming a lower insulating layer on the semiconductor substrate and selectively forming a lower interconnection layer in contact with an upper surface of the lower insulating layer; selectively forming an upper insulating layer in contact with upper surfaces of the lower insulating layer and the lower interconnection layer, and covering a region except an uppermost vertical interconnection region viewed from above including a vertical interconnection for electrically connecting the lower interconnection layer and another interconnection layer above and an internal region of the uppermost vertical interconnection region; and selectively forming an upper conductive layer in contact with exposed upper surfaces of the lower insulating layer, the lower interconnection layer and the upper insulating layer in a region outside a fuse region covering a plane region including the fuse and a neighborhood thereof
With the above-described method, in the step of selectively forming the upper insulating layer, the upper insulating layer is formed in the form having the opening for the vertical interconnection to be formed in the upper insulating. In addition, the vertical interconnection for electrically connecting interconnection layers placed above and below the upper insulating layer and the interconnection layer to be placed on the upper side of the upper insulating layer are formed together as one conductive layer. Thus the number of process steps can be reduced.
In one embodiment of the above-mentioned invention, the step of selectively forming an upper conductive layer includes the steps of: forming the upper insulating layer in contact with upper surfaces of the lower insulating layer and the lower interconnection layer; and removing the upper insulating layer in the uppermost vertical interconnection region and the internal region.
With the above-described method, in the step of selectively forming the upper insulating layer, the upper insulating layer is removed not only in the region corresponding to the opening for the vertical interconnection to be formed in the upper insulating layer but also in the fuse region. Thus the number of process steps can be reduced. Along with the reduction in the number of process steps, the necessary amount of mask material can be reduced as the number of etching processes can be reduced.
In the above-mentioned invention, the step of selectively forming an upper conductive layer preferably includes a step of forming the upper conductive layer outside of the fuse region at a distance not shorter than the thickness of the coating intended to be formed on the upper conductive layer from an outline of the fuse region.
With the above-de
Terashima Tomohide
Yamamoto Fumitoshi
Yamashita Yasunori
Foong Suk-San
Fourson George
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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