Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-02-28
2003-07-15
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S312000, C430S313000, C430S325000, C430S330000, C430S394000
Reexamination Certificate
active
06593063
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a fine resist pattern and a method of manufacturing a semiconductor device using the finely isolated resist pattern, and further relates to a semiconductor device manufactured according to the method.
2. Background Art
As the semiconductor devices have been highly integrated, interconnections and isolation widths required in their manufacturing processes has become very fine. In general, a fine pattern is formed according to a method wherein a resist pattern is formed by a photolithographic technique, and various underlying thin films are respectively etched through the thus formed pattern as a mask.
For the formation of a fine pattern, the photolithographic technique is thus very important. The photolithographic technique includes resist coating, mask alignment, exposure to light, and development. This technique has a limit on the fineness due to the restriction imposed on the wavelength of the exposing light.
Further, the conventional lithographic process has a difficulty in controlling an etching resistance of a resist, making it impossible to fully control a surface profile so that the etched pattern is roughened on the surfaces of side walls by the control of the etching resistance.
As described above, when using the conventional photolithographic technique comprising light exposure, it has been difficult to form a fine resist pattern which exceeds the limit of the wavelength. In order to improve the situation, the present inventors have found a new method to form a fine resist pattern which is beyond the wave length limitation as presented in the Japanese patent publication H10-73927, which corresponds to U.S. patent application Ser. No. 09/049,072 filed Mar. 27, 1998. The present invention aims to further improve the former invention.
SUMMARY OF THE INVENTION
The present invention provides a technique which realize the formation of a finely isolated resist pattern for forming a fine isolation pattern or a fine hole pattern exceeding the wavelength limit. The present invention also provides a technique of roughening the surfaces of side walls of a pattern after etching, which has been difficult in control according to the conventional lithographic technique.
Further, the present invention provides a method for manufacturing a semiconductor device by use of the technique of forming a finely isolated resist pattern, and also provides a semiconductor device manufactured by the method.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a first resist layer is formed on a semiconductor base layer, and the first resist layer is made of a first resist and capable of generating an acid. A first resist pattern is formed from said first resist layer by developing in a reduced developing time, and said first resist pattern is capable of generating an acid. A second resist layer is formed on said first resist pattern, and said second resist layer is capable to undergo crosslinking reaction in the presence of an acid. A crosslinked film is formed at a portion of said second resist layer contacting with said first resist pattern by the agency of an acid fed from said first resist pattern. A second resist pattern is formed by removing non-crosslinked portions of said second resist layer. Finnaly, said semiconductor base layer is etched through said second resist pattern working as a mask.
In another aspect of the present invention, in the method, said reduced developing time is in the range of time where the final dimension of said first resist pattern vary depending on the developing time.
In another aspect of the present invention, in the method, said reduced developing time is in the range of time where the final dimension of said first resist pattern is larger more than 10 nm than when developed with usual developing time where final dimension comes of the resist pattern to be substantially constant.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 4024030 (1977-05-01), Burov et al.
patent: 5545512 (1996-08-01), Nakato
patent: 5744286 (1998-04-01), Choi
patent: 5858620 (1999-01-01), Ishibashi et al.
patent: 6-250379 (1994-09-01), None
patent: 10-73927 (1998-03-01), None
patent: 11-204399 (1999-07-01), None
Ishibashi Takeo
Tanaka Mikihiro
Baxter Janet
Mitsubishi Denki & Kabushiki Kaisha
Walke Amanda C.
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