Method of manufacturing a semiconductor device having a pattern

Details Method of manufacturing a semiconductor device having a pattern Method of manufacturing a semiconductor device having a pattern

1975-09-12

1977-07-12

Drummond, Douglas J.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156656, 156659, 204 32R, 204 38A, H01L 21441

Patent

active

040352064

ABSTRACT:
A method of manufacturing a semiconductor device having a pattern of conductors, according to which method an auxiliary layer is formed which consists of two different sub-layers in which the negative of the desired pattern is provided and which is covered with a metal layer, in which the auxiliary layer and the said metal layer are then removed selectively.
The method is characterized in that the auxiliary layer comprises a lowermost layer of an anodically oxidizable metal and an uppermost layer of the oxide of the said metal and may be used in the manufacture of semiconductor devices, especially transistors for very high frequencies and integrated circuits.

REFERENCES:
patent: 3642548 (1972-02-01), Eger
patent: 3759798 (1973-09-01), Graff et al.
patent: 3778689 (1973-12-01), Bodway
patent: 3825453 (1974-07-01), Black et al.
patent: 3827949 (1974-08-01), Platter et al.

Affiliated with

Also associated with

Rating

Method of manufacturing a semiconductor device having a pattern does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor device having a pattern , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device having a pattern will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-486118