Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-03-02
2002-11-12
Whitehead, Jr., Carl (Department: 1763)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S443000, C438S444000, C438S445000
Reexamination Certificate
active
06479368
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device, in which the depth of a divot in the shallow trench isolation can be controlled.
In a typical process of forming a shallow trench isolation (hereinafter referred to as “STI”), a nitride liner is formed on the thermally oxidized film on the surface of a shallow trench. The nitride liner is so formed to prevent oxidization of the silicon sidewall of the collar region of a deep storage trench. TEOS oxide is then deposited in the shallow trench by means of LPCVD. As a result, a STI is formed which isolates adjacent elements from one another.
As may be seen from
FIG. 1
, a nitride liner
1
is formed in a shallow trench in order to prevent oxidation of the silicon sidewall of the collar oxide region
4
of a deep storage trench
2
. As shown in
FIG. 1
, the deep storage trench
2
is covered with an STI
3
. Where the silicon sidewall of the collar oxide region
4
oxidized, a bird's beak of SiO
2
would grow to generate a stress and cause dislocation of silicon. The nitride liner laid on the bottom of the STI
3
acts as a barrier, which prevents oxygen from diffusing into the trench collar
4
. Thus, the nitride liner greatly reduces the defects in silicon.
However, the STI nitride liner makes it easy for etchant to attack the near-top part of the trench and the near-corner part of the active layer in the wet etching which is performed later to remove the pad nitride film on the element regions. The nitride liner on the upper part of the STI is inevitably etched while the pad nitride film is being etched with hot phosphoric acid. A removing of the pad nitride film is typically accompanied by over-etching for 5 to 10 minutes.
The nitride liner on the upper part of the STI is etched by this over-etching, whereby a small recess known as “divot” is formed in the top edge of the STI. The divot exposes the oxide thermally grown on the sidewall of the shallow trench and the surface of the LPTEOS layer. The etchant invades the recess, etching the oxide during the etching of the pad oxide and gate-sacrificing oxide. Inevitably, the etchant deepens the divot toward the corners of the active region and expands the divot in the horizontal direction.
It is difficult to control this isotropic etching of the near-corner part of the active region. The off current therefore changes greatly, making it impossible to lengthen the charge-holding time.
FIG. 2
is a schematic representation of the divot formed in the top of the STI. Numeral
10
in
FIG. 2
indicates the divot expanded.
The off current depends upon the conductivity of the corner parts of the active region, due to the reduced width of the semiconductor device and also to the electric field concentrated at the corner parts of the active region. The off current is much influenced by the geometrical shapes of the corner parts and the area over which the corner parts overlap the gate conductor (i.e., word line). The overlapping area is determined by the depth of the divot formed on the STI upon completion of the etching of the pad oxide and gate-sacrificing oxide.
Experiments and model simulation have indicated that the threshold voltage (Vt) of a field-effect transistor decreases about 1 mV each time the depth of the divot increases one angstrom.
FIG. 3
shows the results of the model simulation, and
FIG. 4
shows the values actually measured.
Generally, the divot is observed to be 300 angstroms deep. The threshold voltage Vt which corresponds to the depth of 300 angstroms causes, as seen from
FIG. 5
, a change of more than three orders in the off current and increased incidence of retention time fails.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased.
Another object of the invention is to provide a semiconductor device which is manufactured by such a method.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a trench in a semiconductor substrate, for isolating elements; forming a nitride film on a surface of the trench; depositing mask material on an entire surface of the semiconductor substrate to fill the trench with the mask material; etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate; removing an exposed upper portion of the nitride film formed on the surface of the trench; removing the mask material from the trench; filling the trench with element-isolating material, thereby forming an element-isolating region; and forming a transistor in an element region isolated from another element region by the element-isolating region.
According to the present invention, there is provided a semiconductor conductor device which comprises: a semiconductor substrate; an element-isolating region formed by filling element-isolating material in a trench formed in the semiconductor substrate; and a transistor formed in an element region isolated from another element region by the element-isolating region, wherein a nitride film is provided on an entire surface of the trench except an upper part of the surface.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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S. Wolf et al. “Silicon Processing for the VLSI Era”, vol. 1-Process Technology, p. 428.
Gambino Jeffrey P.
Ho Herbert
Mandelman Jack A.
Morikado Mutsuo
Banner & Witcoff , Ltd.
Jr. Carl Whitehead
Novacek Christy
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