Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-09
2002-07-23
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000, C257S354000, C257S394000, C257S396000, C257S409000, C257S492000, C257S496000
Reexamination Certificate
active
06424010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and specifically to a semiconductor device having a semiconductor layer disposed on a substrate with an insulating layer therebetween, and a method of manufacturing the same.
2. Background Art
A so called SOI (Semiconductor on Insulator) structure is known as the one having a semiconductor layer placed on a substrate with an insulating layer therebetween in an attempt to reduce the junction capacitance, to improve the breakdown voltage for isolating elements from each other, or to prevent the turn on or latch up of a parasitic thyristor. An MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed at the semiconductor layer of the structure is generally referred to as SOI-MOSFET.
As shown in
FIG. 32
, the SOI-MOSFET is built at a semiconductor layer (hereinafter referred to as SOI layer)
105
deposited on a substrate
1
with an insulating layers
3
therebetween. Specifically, the SOI-MOSFET is constituted of a drain region
105
a
and a source region
105
b
formed at SOI layer
105
, and a gate electrode layer
109
placed on a region
105
c
(hereinafter referred to as channel formation region) between drain region
105
a
and source region
105
b
and opposite to channel formation region
105
c
with a gate insulating layer
7
therebetween.
Drain region
105
a
and source region
105
b
of the SOI-MOSFET conventionally have a low breakdown voltage since the potential of SOI layer
105
(hereinafter conveniently referred to as body potential) is floating.
More specifically, in the case of n channel, when voltage is applied to gate electrode layer
109
to form a channel at the surface of channel formation region
105
c
, electrons move from source region
105
b
toward drain region
105
a
. Impact ionization caused by the electrons generates a number of electron-hole pairs in the vicinity of the edge of drain region
105
a
. Although the electrons are removed from drain region
105
a
to the outside of SOI layer
105
, the holes accumulate in SOI layer
105
because of the floating state of SOI layer
105
.
Consequently, when a positive voltage is applied to SOI layer
105
, source/drain regions
105
a
and
105
b
and channel formation region
105
c
are forward biased. Accordingly, current easily flows between drain region
105
a
and source region
105
b
and source drain breakdown voltage decreases.
A proposed element isolation method for improving the source-drain breakdown voltage is field shield isolation (hereinafter referred to as FS isolation).
FIG. 33
is a bird's eye view illustrating a structure of an SOI-MOSFET to which the FS isolation structure is applied.
FIG. 34A
is a schematic plan view of the MOSFET portion viewed in the direction of the arrow H of
FIG. 33
, and
FIG. 34B
is a schematic plan view along the F—F line of FIG.
34
A.
Referring chiefly to
FIG. 33
, an SOI layer
105
is formed on a silicon substrate
1
with a buried insulating layer
3
interposed. As described in relation to
FIG. 32
, an MOSFET constituted of source/drain regions
105
a
,
105
b
and a gate electrode layer
109
is formed at SOI layer
105
.
Gate electrode layer
109
extends in a region opposite to SOI layer
105
with a gate insulating layer
7
therebetween while keeping a prescribed gate length (FIG.
34
A).
The FS isolation structure is formed to have an FS plate
11
opposite to SOI layer
105
at an edge of the region where the MOSFET is formed with an intervening insulating layer. According to the method of isolating transistors by the FS isolation method, the potential of SOI layer
105
under FS plate
11
is fixed by applying a prescribed voltage to FS plate
11
for electrically isolating devices such as transistors that are adjacent to each other.
The voltage applied to FS plate
11
is, for example, 0V for an nMOSFET, and Vcc (power supply voltage) for a pMOSFET.
A body contact
23
for drawing out potential from SOI layer
105
is provided opposite to the MOSFET formation region with SOI layer
105
under FS plate therebetween.
By providing body contact
23
on the opposite side of the MOSFET formation region with the FS isolation therebetween, holes generated by the impact ionization can be drawn out from the body contact while electrical isolation between edges of the source and the drain of adjacent transistors is maintained. The source drain breakdown voltage can be improved since holes in SOI layer
105
can be drawn out.
However, if the body potential is fixed by providing body contact
23
(body fix), an advantage specific to the SOI-MOSFET of a small substrate bias effect is lost. Further, a problem arises that an advantage of the SOI structure of high speed and low power consumption is decreased. The problem is hereinafter described in detail.
FIG. 35
is a cross sectional view schematically showing a structure of a transistor formed at a normal semiconductor substrate (hereinafter referred to as bulk transistor). Referring to
FIG. 35
, the bulk-transistor includes a drain region
205
a
and a source region
205
b
formed to define a channel region
205
e
at a semiconductor substrate
201
, and a gate electrode layer
209
formed on the region therebetween with an intervening gate insulating layer
207
.
The substrate bias effect described above refers to increase in threshold voltage Vth caused by a depletion layer
205
d
extending toward substrate
201
when a junction of source/drain regions
205
a
and
205
b
and substrate
201
is reverse biased. If the channel length of the bulk-transistor is long, threshold voltage Vth increases according to the equation below.
Vth
=
V
FB
+
2
φ
F
+
2
ε
S
ε
O
q
N
A
(
2
φ
F
+
V
B
)
C
ox
V
FB
: flat band voltage
φ
F
: built-in potential of channel 205e
ε
O
: dielectric constant in vacuum
ε
S
: relative dielectric of silicon
q
: a charge amount
N
A
: concentration of impurities in channel 205e
C
OX
: gate capacitance
V
FB
: flat band voltage
&phgr;
F
: built-in potential of channel
205
e
&egr;
O
: dielectric constant in vacuum
&egr;
s
: relative dielectric of silicon
q: a charge amount
N
A
: concentration of impurities in channel
205
e
C
OX
: gate capacitance
Variation of threshold voltage Vth of the bulk-transistor according to substrate bias V
B
is shown in FIG.
36
.
If the MOSFET is formed at a floating SOI layer
105
shown in
FIG. 37
, substrate bias V
B
is applied to SOI layer
105
via a buried oxide film
3
. Therefore, substrate bias V
B
has little effect on threshold voltage Vth. As shown in
FIG. 38
, threshold voltage Vth scarcely changes with substrate bias V
B
.
However, if substrate bias V
B
is directly applied to SOI layer
105
as shown in
FIG. 39
to fix the body, the junction is reverse biased when substrate bias V
B
is applied as in the bulk-transistor, resulting in increase in threshold voltage Vth due to a depletion layer
105
d
extending into a channel formation region
105
c
even in the SOI-MOSFET.
If threshold voltage Vth increases as described above, drain current Id decreases to make it difficult to operate an LSI (Large Scale Integrated Circuit) at a high speed.
In addition, the high threshold voltage Vth prevents reduction of supply voltage, and power consumption increases.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device having an excellent source drain breakdown voltage as well as a small substrate bias effect operating at high speed and with low power consumption, and a method of manufacturing such a semiconductor device.
A semiconductor device according to the present invention includes a semiconductor layer, a gate insulation type field effect transistor, and a conductive layer for isolation. The semiconductor layer is disposed on a substrate with an insulating layer therebetween
Iwamatsu Toshiaki
Maeda Shigenobu
Yamaguchi Yasuo
Eckert II George C.
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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