Method of manufacturing a semiconductor device by forming insula

Details Method of manufacturing a semiconductor device by forming insula Method of manufacturing a semiconductor device by forming insula

1989-06-20

1991-03-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 73, 437194, 437927, 357 65, H01L 21441, H01L 2176

Patent

active

050010794

ABSTRACT:
Spaced-apart regions (2) each having top (2a) and side walls (2b) meeting at an edge (20) are defined on a surface (1a) of a substructure (1) forming part of the device. A layer (3) of insulating material is provided over the surface (1a) and regions (2), so that the insulating material is provided preferentially at the edges (20) of the regions (2) to form adjacent the edges (20) portions (31) of the insulating material which overhang the underlying insulating material (32) provided on the surface (1a) and define a void therein. The insulating material layer (3) is then etched anisotropically to expose the top walls (2a). During the anisotropic etching the overhanging portions (31) initially mask the underlying insulating material provided on the surface (1a) so that the etching of the underlying insulating material is controlled by the etching away of the overhanging portions (31) and when the top walls (2 a) are exposed relatively gently sloping spacers or portions (30) of the insulating material remain on the side walls (2b). A further insulating material layer (4) may then be provided over the structure.

REFERENCES:
patent: 4755477 (1988-07-01), Chao
De Le Moneda, "Processes to Reduce and Control the P-Type Doping Conc. at . . ." IBM Technical Disclosure Bulletin, vol. 25, No. 11B, Apr. 1983, pp. 6131-6142.

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