Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-02-14
2004-10-26
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S096000, C438S155000, C438S163000, C438S164000, C438S153000
Reexamination Certificate
active
06808964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, a liquid crystal display device, a process for a semiconductor device and a process for a liquid crystal display device, in particular to a semiconductor device, a liquid crystal display device, a process for a semiconductor device and a process for a liquid crystal display device which include field effect transistors having an LDD (Lightly Doped Drain) structure.
2. Description of the Background Art
Conventionally, a liquid crystal display device, which utilizes thin film field effect transistors formed on a glass substrate, has been known as one of liquid crystal display devices. A glass substrate where thin film field effect transistors are formed in such a liquid crystal display device is shown in FIG.
47
.
FIG. 47
is a cross section diagram showing a conventional liquid crystal display device. Referring to
FIG. 47
, a liquid crystal display device is described.
Referring to
FIG. 47
, an n type thin film field effect transistor
119
and a p type thin film field effect transistor
120
are formed in a drive circuit region on a glass substrate
101
in a liquid crystal display device. In addition, a capacitor
121
and a thin film field effect transistors
122
for a pixel are formed in a display pixel region.
In the drive circuit region, a base film
102
is formed on the glass substrate
101
. A silicon oxide film is used for this base film n
+
type impurity regions
103
a
,
103
b
, n
−
type impurity regions
104
a
,
104
b
and a channel region
106
a
are formed on the base film
102
by using the same semiconductor film. A gate insulating film
107
a
is formed on the channel region
106
a
. A gate electrode
108
a
is formed on the gate insulating film
107
a
. The source/drain regions are formed of n
+
type impurity regions
103
a
,
103
b
and n
−
type impurity regions
104
a
,
104
b
. The n type thin film field effect transistor
119
is formed of those n
+
type impurity regions
103
a
,
103
b
, n
−
type impurity regions
104
a
,
104
b
, channel region
106
a
, gate insulating film
107
a
and gate electrode
108
a.
In addition, p type impurity regions
105
a
,
105
b
and a channel region
106
b
are formed on the base film
102
by using the same semiconductor film. A gate insulating film
107
b
is formed on the channel region
106
b
. A gate electrode
108
b
is formed on the gate insulating film
107
b
. A p type thin film field effect transistor
120
is formed of those p type impurity regions
105
a
,
105
b
, channel region
106
b
, gate insulating film
107
b
and gate electrode
108
b
. An interlayer insulating film
110
is formed on those n type thin film field effect transistor
119
and p type thin film field effect transistor
120
. In the regions located above the n
+
type impurity regions
103
a
,
103
b
and the p type impurity regions
105
a
,
105
b
, contact holes
111
a
to
111
d
are formed in the interlayer insulating film
110
. Metal wires
112
a
to
112
d
are formed so as to extend from the inside of the contact holes
111
a
to
111
d
to the upper surface of the interlayer insulating film
110
. A passivation film (not shown) is formed on the metal wires
112
a
to
112
d
. A flatting film
113
is formed on the passivation film.
In the display pixel region, a capacitor electrode
109
is formed on the base film
102
. Another capacitor electrode
108
e
is formed above the capacitor electrode
109
via an insulating film
107
e
as the dielectric film. A capacitor
121
is formed of these capacitor electrodes
109
,
108
e
and insulating film
107
e
. An n
+
type impurity region
103
c
is formed, as the conductive region, on the base film
102
so as to adjoin the capacitor electrode
109
. In addition, n
+
type impurity regions
103
d
to
103
f
, n
−
type impurity regions
104
d
to
104
g
and channel regions
106
c
,
106
d
are formed on the base film
102
by using the same semiconductor film. Gate insulating films
107
c
,
107
d
are formed on the channel regions
106
c
,
106
d
, respectively. Gate electrodes
108
c
and
108
d
are formed on the gate insulating films
107
c
,
107
d
, respectively. In this way, one thin film field effect transistor is formed of the n
+
type impurity regions
103
d
,
103
e
, the n
−
type impurity regions
104
d
,
104
e
, the channel region
106
c
, the gate insulating film
107
c
and the gate electrode
108
c
. In addition, another thin film field effect transistor is formed of the n
+
type impurity regions
103
e
,
103
f
, the n
−
type impurity regions
104
f
,
104
g
, the channel region
106
d
, the gate insulating film
107
d
and the gate electrode
108
d
. The thin film field effect transistors
122
for pixels include those two thin film field effect transistors.
An interlayer insulating film
110
is formed on the capacitor
121
and the thin film field effect transistors
122
for a pixel. In the regions located above the n
+
type impurity regions
103
c
,
103
d
and
103
f
, contact holes
111
e
to
111
g
are formed in the interlayer insulating film
110
. Metal wires
112
e
and
112
f
are formed so as to extend from the inside of the contact holes
111
e
to
111
g
to the upper surface of the interlayer insulating film
110
. A passivation film (not shown) is formed on the metal wires
112
e
and
112
f
. A flatting film
113
is formed on the passivation film. In the region located above the metal wire
112
e
, a contact hole
114
is formed in the flatting film
113
and the passivation film. A pixel electrode
115
is formed so as to extend from the inside of the contact hole
114
to the upper surface of the flatting film
113
by using ITO or the like.
FIGS. 48
to
51
are cross section diagrams for describing a process for the liquid crystal display device as shown in FIG.
47
. Referring to
FIGS. 48
to
51
, a process for a liquid crystal display device is described.
First, a base film
102
such as a silicon oxide film is formed on a glass substrate
101
. An amorphous silicon film is formed on this base film
102
. A polysilicon film is formed by annealing this amorphous silicon film using a laser or the like. A resist film is formed on this polysilicon film. A channel pattern is formed by carrying out an exposure to light and development processing on this resist film. Then, by using, as a mask, the resist film where the channel pattern is formed, the polysilicon film is etched so as to form polysilicon films
127
a
to
127
c
(see
FIG. 48
) and polysilicon film to be a capacitor electrode. After that, the resist film is removed. By implanting conductive impurities into the polysilicon film to be the capacitor electrode, a conductive film
128
(see
FIG. 48
) is formed. An insulating film to be a gate insulating film is formed on the polysilicon films
127
a
to
127
c
and the conductive film
128
. A conductive film is formed on this insulating film. A resist film is formed on this conductive film. A gate pattern is formed in the resist film by carrying out exposure to light and development processing. By using, as a mask, the resist film where the gate pattern is formed, gate electrodes
108
a
to
108
d
(see
FIG. 48
) and a capacitor electrode
108
e
(see
FIG. 48
) are formed by carrying out wet etching. After that, the resist film is removed. Then, by using the gate electrodes
108
a
to
108
d
and the capacitor electrode
108
e
as a mask, the insulating film is etched so as to form the gate insulating film
107
a
to
107
b
(see
FIG. 48
) and the insulating film
107
e
(see
FIG. 48
) as the dielectric film. In this way, a structure as shown in
FIG. 48
is gained.
After that, as shown in
FIG. 49
, a resist film
130
b
is formed so as to cover the region where the p type thin film field effect transistor
120
(see
FIG. 47
) is to be formed and at the same time resist film
130
a
,
130
c
and
130
d
is formed which becomes a
Hayashi Masami
Murai Ichiro
Flynn Nathan J.
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Sefer Ahmed N.
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