Method of manufacturing a semiconductor device and...

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Reexamination Certificate

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C430S312000, C430S328000, C430S330000, C430S270100, C430S170000, C430S189000, C430S141000, C134S001300

Reexamination Certificate

active

06566040

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a hyperfine pattern beyond the limit of the lithography technology, and to a semiconductor device manufactured by the manufacturing method.
2. Background Art
The present inventors proposed a method of forming a fine resist pattern that is beyond the limit of the exposure-based photolithography technology (for instance, U.S. patent application Ser. No. 08/785,846 filed on Jan. 24, 1997, or Japanese Patent Application Laid-Open No. 10-73927).
FIG. 10
outlines this method. In this method, in step
11
shown in
FIG. 10
, a first resist pattern
3
capable of supplying acid is formed on a semiconductor substrate
1
and then a second resist in which a crosslinking reaction is caused by acid is applied to the pattern
3
including the surface of a hole
4
. In step
12
, a crosslinked film (organic frame)
7
is formed on the side wall of the first resist pattern
3
by a heat treatment and resulting dissolution. In this manner, the inner diameter of the hole
8
or the separation width of a line pattern is reduced.
In the above method, the thickness of the crosslinked film (organic frame)
7
can be controlled by adjusting the temperature or time of the heat treatments (mixing baking) of the first and second resists or the material composition of the second resist. However, where the hole inner diameter or the separation width of a line pattern is made extremely small, there may occur an event that residues
10
or the like of the second resist remain in the hole
8
and other portions (shown as step
13
), and will obstruct satisfactory pattern formation.
Where the hole inner diameter is further reduced to 0.1 &mgr;m□ (a square each side of which is 0.1 &mgr;m long) or less, there may occur an event that residues remain in the hole
8
or the interface portion with the semiconductor substrate
1
in the hole
8
at the time of cleaning and drying of a second resist rinse-removal step and will cause etching defects. This is another problem of the conventional method.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above problems and thereby provide a method of manufacturing a semiconductor device which can make the diameter of a resist hole pattern or the separation width of a resist line pattern extremely small, as well as a semiconductor device that is manufactured by such a manufacturing method. Such a hyperfine pattern is applicable to manufacture of LSI semiconductor devices, liquid crystal display panels, etc.
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a first resist pattern of a first resist, that is capable of generating acid, is formed on a semiconductor base member. A film of a second resist is formed on the first resist pattern, and the second resist is such that a crosslinking reaction occurs therein under presence of acid. A crosslinked film is formed in a portion of the film of the second resist that is in contact with the first resist pattern by causing the first resist pattern to supply acid to the film of the second resist. A second resist pattern is formed in which the first resist pattern is covered with the crosslinked film by removing an uncrosslinked portion of the film of the second resist. A heat treatment is performed to cause thermal reflow of the crosslinked film, to thereby reduce a gap in the second resist pattern. Further, the semiconductor base member is etched by using, as a mask, the second resist pattern having the reflow-subjected crosslinked film.
In another aspect of the present invention, in the manufacturing method, between the heat treatment and the etching, the second resist pattern may be cleaned with pure water or a mixed solvent of pure water and an organic solvent, to remove a residue in a portion that is not in contact with the first resist pattern.
In another aspect of the present invention, in the method of manufacturing a semiconductor device, a heat treatment may be performed, after forming the second resist pattern including the crosslinked film, to render the crosslinked film insoluble in pure water or a mixed solvent of pure water and an organic solvent. Further, cleaning the second resist pattern may be cleaned with pure water or the mixed solvent of pure water and the organic solvent, to thereby remove a residue in a portion that is not in contact with the first resist pattern. Thereafter, the semiconductor base member may be etched by using the residue-removed second resist pattern as a mask.
Other and further objects, features and advantages of the invention will appear more fully from the following description.


REFERENCES:
patent: 4501806 (1985-02-01), Watanabe et al.
patent: 5324550 (1994-06-01), Yamaguchi et al.
patent: 5342727 (1994-08-01), Vicari et al.
patent: 5527662 (1996-06-01), Hashimoto et al.
patent: 5545512 (1996-08-01), Nakato
patent: 5858620 (1999-01-01), Ishibashi et al.
patent: 6180320 (2001-01-01), Saito et al.
patent: 5-160019 (1993-06-01), None
patent: 5-166717 (1993-07-01), None
patent: 5-241348 (1993-09-01), None
patent: 6-104171 (1994-04-01), None
patent: 6-250379 (1994-09-01), None
patent: 7106237 (1995-04-01), None
patent: 7-134422 (1995-05-01), None
patent: 10-73927 (1998-03-01), None
patent: 98-5636 (1998-03-01), None
“Electron-Beam, X-Ray, and Ion-Beam Technology: Submicrometer Lighographies VII” by Arnold W. Yanof, Proceedings of SPIE—The International Society for Optical Engineering, Mar. 2-4, 1988, vol. 923, pp. 158-171.
“Deep UV ANR Photoresists for 248 nm Excimer Laser Photolighography” by James Thockeray, et al., Proceedings of SPIE—The International Society for Optical Engineering, 1989, vol. 1086, pp. 34-47.

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