Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-07-02
2010-10-19
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S294000, C438S296000, C438S424000, C438S589000, C257SE21546, C257SE21553
Reexamination Certificate
active
07816228
ABSTRACT:
In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.
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patent: 2004247463 (2004-09-01), None
patent: 1020060013122 (2006-02-01), None
Choi Yong-Lack
Kim Na-Young
Kim Sung-Hwan
Oh Chang-Woo
Garber Charles D
Roman Angel
Samsung Electronics Co,. Ltd.
Volentine & Whitt PLLC
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