Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-01-23
2007-01-23
Pert, Evan (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S486000, C438S487000
Reexamination Certificate
active
10978462
ABSTRACT:
In a method of manufacturing a semiconductor device, after a lateral growth region107is formed by using a catalytic element for facilitating crystallization of silicon, the catalytic element is gettered into a phosphorus added region108by a heat treatment. Thereafter, a gate insulating film113is formed to cover active layers110to112formed, and in this state, a thermal oxidation step is carried out. By this, the characteristics of an interface between the active layers and the gate insulating film can be improved while abnormal growth of a metal oxide is prevented.
REFERENCES:
patent: 5550070 (1996-08-01), Funai et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5648277 (1997-07-01), Zhang et al.
patent: 5753544 (1998-05-01), Cho et al.
patent: 6066518 (2000-05-01), Yamazaki
patent: 6124154 (2000-09-01), Miyasaka
patent: 6140166 (2000-10-01), Ohtani et al.
patent: 6162704 (2000-12-01), Yamazaki et al.
patent: 6165824 (2000-12-01), Takano et al.
patent: 6232205 (2001-05-01), Ohtani
patent: 6242290 (2001-06-01), Nakajima et al.
patent: 6255195 (2001-07-01), Linn et al.
patent: 6355509 (2002-03-01), Yamazaki
patent: 6368904 (2002-04-01), Yamazaki
patent: 6383852 (2002-05-01), Zhang et al.
patent: 6432756 (2002-08-01), Ohtani et al.
patent: 6444534 (2002-09-01), Maszara
patent: 6461943 (2002-10-01), Yamazaki et al.
patent: 6465288 (2002-10-01), Ohnuma
patent: 6479333 (2002-11-01), Takano et al.
patent: 6551907 (2003-04-01), Ohtani
patent: 6624049 (2003-09-01), Yamazaki
patent: 6639245 (2003-10-01), Gotoh et al.
patent: 6695955 (2004-02-01), Hwang et al.
patent: 6893503 (2005-05-01), Ohnuma et al.
patent: 05-109737 (1993-04-01), None
patent: 07-130652 (1995-05-01), None
patent: 07-135318 (1995-05-01), None
patent: 07-321339 (1995-12-01), None
patent: 08-078329 (1996-03-01), None
R. Shimokawa and Y. Hayashi, “Characterization of High-Efficiency Cast-Si Solor Cell Wafers by MBIC Measurement,” Japanese Journal of Applied Physics, vol. 27, No. 5, May 1988, pp. 751-758.
Ohtani Hisashi
Yamazaki Shunpei
Pert Evan
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3800260