Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-11-22
2005-11-22
Sarkar, Asok Kumar (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C438S689000, C438S778000
Reexamination Certificate
active
06967151
ABSTRACT:
Provided is a method of manufacturing a semiconductor device. In the method, an insulation spacer is formed thicker than a target thickness on sidewalls of a gate line formed on a semiconductor substrate. The thickness of the insulation spacer is adjusted by means of a wet etching process, so that aspect ratios of spaces between gate lines become smaller to control opening widths of junction areas. The method enhances fill-up characteristics of insulation layers between the gate lines, and improves the reliability of process and an electrical characteristic of device by controlling the opening widths of junction areas.
REFERENCES:
patent: 5238872 (1993-08-01), Thalapaneni
patent: 5422295 (1995-06-01), Choi et al.
patent: 5766991 (1998-06-01), Chen
patent: 6350665 (2002-02-01), Jin et al.
Park Sang Wook
Song Pil Geun
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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