Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

2003-01-17

2004-08-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C430S314000, C430S316000

Reexamination Certificate

active

06774048

ABSTRACT:

RELATED APPLICATIONS
The present application claims priority from Korean Patent Application No. 2002-31421, filed Jun. 4, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to methods for manufacturing semiconductor devices and, more particularly, to a method for manufacturing a semiconductor device having an improved quality by increasing an adhesion and improving an interface characteristic between a silicon nitride layer and an oxide layer formed thereon.
BACKGROUND OF THE INVENTION
Recently, the design of semiconductor devices has experienced rapid progress as information media and devices such as computers are widely used. This progress has required semiconductor devices that can function at high operating speeds and to have large storage capacities. In order to satisfy such requirements, semiconductor devices with increased density, reliability, and response time speed are under development. To increase the degree of integration, the cell size should be reduced and, with the reduction in the cell size, the size and margin of all kinds of patterns formed on a semiconductor substrate also should be reduced. On the other hand, the aspect ratio of each component in the semiconductor device gradually increases.
A polysilicon gate structure having a good electric characteristic, reliability and degree of integration was adopted as a driving device from the initial VLSI. Therefore, the polysilicon gate structure has been largely developed in industrial fields such as LSI's for micro-computers or devices with high-density memories, and is now widely used in various fields. Because the melting point of polysilicon is high, a self-align method can be applied during the formation of a gate electrode along with a diffusion region of source and drain when using polysilicon. In addition, after patterning the gate electrode using polysilicon, a thermal oxidation of polysilicon may also be performed. Accordingly, damage generated at the edge portion of the gate electrode due to reactive ion etching may be compensated for. When an electric voltage is applied to the gate electrode, a high fringe electric field at the edge portion of the gate electrode is lowered to increase the reliability of the semiconductor device.
Meanwhile, the design rule of recently developed and highly integrated semiconductor devices has been reduced to about 0.15 &mgr;m or less. Accordingly, a self-align method is widely used in order to ensure a BC processing margin. A method of forming a contact hole of a semiconductor device by the self-align method will be described in detail below with reference to the attached drawings.
FIGS. 1A-1E
are cross-sectional views illustrating a method of forming a contact hole of a semiconductor device in accordance with a conventional method.
Referring to
FIG. 1A
, a gate oxide layer
21
is formed on a semiconductor substrate
11
such as a silicon substrate. Then, a conductive layer and a capping insulation layer are subsequently formed on the gate oxide layer
21
. The conductive layer is a doped polysilicon layer or a polycide layer. The polycide layer includes a doped polysilicon layer and a refractory metal silicide layer. As the refractory metal silicide layer, a tungsten silicide layer, a titanium silicide layer, a cobalt silicide layer, etc., are widely applied.
The capping insulation layer is preferably comprised of silicon nitride. A silicon nitride layer has a high etching selectivity with respect to an oxide layer. Then, the capping insulation layer and the conductive layer are continuously patterned to form parallel gate patterns
37
with a predetermined spacing on a predetermined region of the gate oxide layer
21
. Each of the gate patterns
37
includes an integrated conductive layer pattern
31
and a capping insulation layer pattern
32
. The conductive layer pattern
31
functions as a gate electrode.
Referring to
FIG. 1B
, a silicon nitride layer is formed on the entire surface of the substrate on which the gate patterns
37
are formed. Then, the silicon nitride layer is etched anisotropically to form a spacer
33
at the sidewall portions of the gate patterns
37
. At this time, the gate oxide layer
21
formed between the gate patterns
37
may be over-etched to expose the semiconductor substrate
11
or such that a thinner oxide layer than the initial gate oxide layer
21
remains. When completing the formation of the spacer
33
, the conductive pattern
21
, i.e., the gate pattern, is completely surrounded by a gate oxide layer pattern
22
, the capping insulation layer pattern
32
and the spacer
33
.
During implementation of the anisotropic etching for forming the spacer
33
, the surface portion of the semiconductor device is damaged. Therefore, after completing the anisotropic etching to form the spacer
33
, a thermal oxidation is performed to remove the etching damage. Then, a thin thermal oxide layer is grown on the surface of the semiconductor substrate
11
between the gate patterns
37
. Using the thin thermal oxide layer as a screen oxide layer, ion implantation is conducted to form a source/drain region (not shown) at the surface portion of the semiconductor substrate
11
between the gate patterns
37
.
Referring to
FIG. 1C
, an etching stop layer
34
such as a silicon nitride layer is formed using a chemical vapor deposition (CVD) method. The preferred thickness of the etching stop layer
34
is in a range of from about 70 to about 150 Å. In
FIG. 1C
, the reference symbol G
1
represents a gap size.
Referring to
FIG. 1D
, an interlayer dielectric
41
is formed on the etching stop layer
34
using an insulating material having a good filling characteristic into a concave portion. Conventionally, a high density plasma CVD oxide layer is formed, or a high density plasma CVD oxide layer and a low pressure CVD oxide layer are subsequently integrated to form the interlayer dielectric.
When the plasma CVD method is applied, the interlayer dielectric adheres to an underlying layer with sufficient adhesive power to prevent separation of the thus formed layer at the interface because the reactivity of the plasma is good. However, as the gap size formed by the etching stop layer becomes narrow, a void is formed. Accordingly, a flow fill method has been used recently instead of the plasma CVD method when the gap size formed between patterns is small.
The method of forming an interlayer dielectric using the flow fill method will be described in detail below. According to this method, a layer is formed by reacting silane with hydrogen peroxide gas utilizing, for example, an apparatus named Flow Fill and manufactured by Trikon Co. Ltd. This method is particularly appropriate for filling a small gap formed between patterns of an underlying layer. Silane compounds such as SiH
4
, CH
3
SiH
3
, etc., are reacted with hydrogen peroxide (H
2
O
2
) to produce SiO
2
or (SiOCH)n to form a silicon oxide layer. First, the silane compound and hydrogen peroxide are reacted with each other in gaseous phase to produce a hydroxy silane compound such as Si(OH)
4
or CH
3
Si(OH)
3
. This product generates a liquid phase reaction at the surface portion of the underlying layer to form a polymer though dehydration to deposit an oxide layer of SiO
2
. Accordingly, when using the flow fill method on a layer having a small pattern gap, the generation of the aforementioned void can be avoided, and so this method is now in wide use.
Next, the interlayer dielectric
41
is planarized. A photoresist pattern
51
having a predetermined shape is formed for patterning the planarized interlayer dielectric.
Referring to
FIG. 1E
, an interlayer dielectric pattern
42
is formed and the etching stop layer
34
between the gate patterns
37
is exposed by etching the interlayer dielectric
41
using the photoresist pattern
51
. Thereafter, the exposed etching stop layer
34
is etched to expose the semiconductor substrate
11
between the gate patterns
37
to form a self-a

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