Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-30
2004-09-28
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06797615
ABSTRACT:
The invention relates to a method of manufacturing a semiconductor device by which method a first wiring layer with conductor tracks, among which a number having a width w and a number having a greater width, is formed on a surface of a semiconductor body, after which a first insulating layer is formed on and between the conductor tracks of the first wiring layer by means of a process in which the thickness of the insulating layer formed is dependent on the width of the subjacent conductor tracks, whereupon a capping layer is deposited on the first insulating layer and said capping layer is planarized by means of a polishing treatment. A semiconductor device is formed in this manner.
A method of the kind mentioned in the opening paragraph is known from WO 99/00838, in which the first wiring layer is formed in a layer of polycrystalline silicon. The conductor tracks form, inter alia, gate electrodes of memory and switching transistors.
It is found that a layer is formed which is not equally thick everywhere in the formation of the first insulating layer by means of, for example, a spin-on process. A thinner layer of insulating material is formed on the conductor tracks having a width w, which are present at the areas of the circuits mentioned above, than on the conductor tracks having a greater width, which are present between the circuits mentioned above. This same effect is found to occur in some cases, also if a CVD process is used for forming the first insulating layer. The capping layer deposited on the layer of insulating material has the same thickness everywhere if it is deposited by means of, for example, a CVD process. The capping layer is planarized in the polishing treatment; the layer here is given a planar surface which is parallel to the surface of the semiconductor body. The polishing treatment is continued until a desired thickness has been reached above the conductor tracks having the width w, for example a thickness which renders it possible to form a second wiring layer on the capping layer and which is so small that a capacitive coupling between the two wiring layers is a minimum. Since the thickness of the insulating layer above the wide conductor tracks is greater than above the conductor tracks having the width w, a capping layer will remain above the wider conductor tracks in the polishing treatment which is thinner than the capping layer above the narrower conductor tracks having the width w. If the desired thickness is to be realized above the narrower conductor tracks, the layer above the wider tracks may become so thin that cracks are locally formed there in the capping layer during the polishing treatment; the layer cannot withstand the pressure exerted on the layer during polishing.
The invention has for its object inter alia to solve this problem. According to the invention, the method is for this purpose characterized in that the conductor tracks of the first wiring layer having a width greater than w are formed by a number of mutually parallel strips having a width w, which strips are locally interconnected. It is achieved thereby that the insulating layer is given a thickness, for example during a spin-on process, which is practically the same as the thickness of the layer above the narrower conductor tracks having the width w. It is found in practice then that a capping layer remains in both locations which can withstand the pressure during the polishing treatment.
Open spaces may occur between the conductor tracks with the width w and the wider conductor tracks formed by a number of mutually interconnected strips with the width w. An insulating layer is formed above these open spaces during the spin-on process with a thickness which is greater than that of the layer above the conductor tracks. The upper side of the layer, however, lies closer to the surface of the semiconductor body there than at the areas of the conductor tracks. A capping layer will remain above said open spaces after the polishing treatment which is thicker than the capping layer remaining above the conductor tracks. Cracks may arise in the capping layer also above the open spaces owing to the pressure exerted on the layer during the polishing treatment. The capping layer will then show cracks mainly in those regions where the thickness transition takes place. This problem is solved if plates are formed in the first wiring layer of conducting material provided on the surface between neighboring conductor tracks of the first wiring layer, that are separated by a space having a width larger than w said plates being formed by a number of mutually parallel strips having a width w. The insulating layer above these plates will then have a thickness equal to the thickness of the layer above the conductor tracks. Alternatively, the isolated plates may be formed in a separate layer of insulting material. Preferably all spaces with a width larger than twice the width w are filled up. The spaces are for instance filled with tracks of the same pattern and size as the other conducting tracks.
It is achieved that the insulating layer has the same thickness everywhere and that a capping layer of uniform thickness is formed in the polishing treatment over the entire surface area of the semiconductor body in that it is ensured that the conductor tracks of the first metallization layer having a width w as well as the mutually parallel strips forming the wider conductor tracks and the plates are formed with a mutual distance w each time. Cracks in this layer arising during the polishing treatment are counteracted as much as possible thereby.
Further process steps may take place after the planarization of the capping layer. The planarized capping layer may be provided with contact windows within which conductor tracks of the first wiring layer are exposed, whereupon the planarized capping layer is provided with a second wiring layer with conductor tracks which make contact with conductor tracks of the first wiring layer. An additional advantage of this is that the conductor tracks of the second wiring layer may at the same time serve as interconnections for the mutually parallel strips having a width w which form the conductor tracks of the first wiring layer. An interconnection of said strips in the first wiring layer is made unnecessary thereby.
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Heringa Anco
Lous Erik Jan
Van De Goor Albertus Theodorus Maria
Fawilski Peter
Kilday Lisa
Pert Evan
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