Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-03
2003-01-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S627000, C438S634000, C438S638000
Reexamination Certificate
active
06503830
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device, which includes a forming method of a dual damascene structure using a so-called dual hard mask.
2. Description of the Related Art
In the wiring structure of the dual damascene structure, a silicon oxide layer is used as a connection layer in which a connection hole is formed, an organic film is used as a wiring layer in which groove wiring lines are formed, a silicon oxide film is used as a lower layer hard mask, and a silicon nitride film is used as an upper layer hard mask.
Hereinafter, a method of manufacturing groove wiring lines using a conventional dual hard mask method will be described with reference to manufacturing process sectional views of
FIGS. 3A
to
3
G.
Although not shown, for example, after a semiconductor element, a wiring line and the like are formed on a semiconductor substrate by a well-known semiconductor process technique, an interlayer insulating film covering the semiconductor element, the wiring line and the like is formed. Next, for example, a silicon nitride film for preventing diffusion of copper is formed on the interlayer insulating film, and further, an insulating film in which a groove wiring line is formed, is formed of, for example, a silicon oxide film.
Next, by using a normal forming technique of a groove wiring line, a groove for formation of a wiring line is formed in the silicon oxide film. Then, a barrier layer for preventing diffusion of copper is formed on the inner surface of the groove, and further, after copper is embedded in the inside of the groove through the barrier layer, the surplus copper and barrier layer on the silicon oxide film are removed, and a first wiring line is formed in the inside of the groove. In this way, a base body
110
as shown in
FIG. 3A
is formed.
Thereafter, for example, by a PE-CVD (Plasma Enhancement) (Chemical Vapor Deposition) method, a barrier layer
111
made of a silicon nitride film for preventing diffusion of copper is formed to a thickness of, for example, 50 nm on the base body
110
. Next, for example, by the PE-CVD method, a first insulating film
112
, which becomes a connection layer in which a connection hole is formed, is formed on the barrier layer
111
by forming, for example, a silicon oxide film of a thickness of 500 nm.
Next, for example, by the PE-CVD method, an organic film of a thickness of, for example, 400 nm is formed on the first insulating film
112
so that a second insulating film
113
is formed.
Next, by a chemical vapor deposition (hereinafter referred to as CVD) method or a physical vapor deposition (hereinafter referred to as PVD) method, a lower layer hard mask
114
is formed on the second insulating film
113
by forming, for example, a silicon oxide film of a thickness of 200 nm. Further, an upper layer hard mask
115
of, for example, a silicon nitride film of a thickness of 100 nm is formed on the lower layer hard mask
114
.
Next, although not shown, after a resist mask (not shown) which becomes an etching mask for formation of a groove is formed by resist coating and a lithography technique, the upper layer hard mask
115
is subjected to, for example, anisotropic etching by an etching technique using the resist mask, so that an opening
116
for formation of a wiring groove is formed. Thereafter, the resist mask is removed by a normal resist removal technique Next, as shown in
FIG. 3B
, a resist mask
117
is formed on the hard mask
115
including the inside of the opening
116
by the resist coating technique. Then, an opening
118
for formation of a connection hole is formed in the resist film
117
by the lithography technique.
As an example of the etching conditions of the upper layer hard mask
115
made of the silicon nitride film, for example, a magnetron etching apparatus was used, trifluoromethane (CHF
3
) (supply flow rate was, for example, 20 cm
3
/min), argon (Ar) (supply flow rate was, for example, 200 cm
3
/min) and oxygen (O
2
) (supply flow rate was, for example, 10 cm
3
/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0° C.
Next, as shown in
FIG. 3C
, the resist film
117
is used as a mask, and the lower hard mask
114
is subjected to, for example, anisotropic etching by an etching technique to form a connection hole pattern
119
.
As an example of the etching conditions of the lower layer hard mask
114
made of the silicon oxide film, for example, a magnetron etching apparatus was used, octafluorocyclobutane (C
4
F
8
) (supply flow rate was, for example, 20 cm
3
/min), argon (Ar) (supply flow rate was, for example, 200 cm
3
/min) and oxygen (O
2
) (supply flow rate was, for example, 10 cm
3
/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0° C.
Further, as shown in
FIG. 3D
, the etching is made to proceed while the lower layer hard mask
114
is used as a mask, and the connection hole pattern
119
is formed to extend into the second insulating film
113
made of the organic film. In this etching, since the organic film is etched while the lower mask
114
made of the silicon oxide film is used as the etching mask, the first insulating film
112
made of the silicon oxide film functions as an etching stopper. Besides, in this etching, since the resist mask
117
(see
FIG. 3C
) is also etched and is removed, an etching process for removing only the resist mask
117
is not required.
As an example of the etching conditions of the organic film, for example, an electron cyclotron resonance (hereinafter referred to as ECR) etching apparatus was used, ammonia (NH
3
) (supply flow rate was, for example, 100 cm
3
/min) was used as an etching gas, and the pressure of an etching atmosphere was set to 3 Pa.
Next, as shown in
FIG. 3E
, the wiring groove pattern
116
is formed to extend into the lower hard mask
114
while the upper layer hard mask
115
is used as the etching mask, and a connection hole
121
is formed in the first insulating film
112
while the second insulating film
113
is used as an etching mask. In this etching, over etching for etching the silicon oxide film of a thickness of 500 nm is applied to the upper layer hard mask
115
. Thus, the wiring groove pattern
116
moves back.
Next, as shown in
FIG. 3F
, the upper layer hard mask
115
and the lower layer hard mask
114
are used as etching masks, and a wiring groove
122
is formed in the second insulating film
113
.
Further, as shown in
FIG. 3G
, the first insulating film
112
is used as an etching mask, and the barrier layer
111
made of the silicon nitride film exposed at the bottom of the connection hole
121
is removed by etching. At this time, the upper layer hard mask
115
(see
FIG. 3F
) is also removed at the same time. As an example of the etching conditions of the silicon nitride film, for example, a magnetron etching apparatus was used, trifluoromethane (CHF
3
) (supply flow rate was, for example, 20 cm
3
/min), argon (Ar) (supply flow rate was, for example, 200 cm
3
/min) and oxygen (O
2
) (supply flow rate was, for example, 10 cm
3
/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0° C.
In this way, the wiring groove
122
is formed in the second insulating film
113
, and the connection hole
121
communicating with the first wiring line (not shown) is formed in the first insulating film
112
.
However, in the conventional technique, since etching selectivity to the upper layer hard mask is insufficient, when the wiring groove pattern is formed in the lower layer hard mask while the upper layer hard mask is used as the etching mask, there arises a problem that the wiring groove pattern is formed to be enlarged when the wiring groove pattern formed in the mask is enlarged, the wiring groove forme
Gurley Lynne A.
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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