Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-25
2003-04-29
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000
Reexamination Certificate
active
06555459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a chip-size package (CSP) and a method of manufacturing thereof. The chip-size package is a generic name for packages of a size equal to or slightly larger than the chip size and is a package intended for high-density packaging. The invention relates to a metal post used in the CSP.
2. Description of the Related Art
Hitherto, in the field, a structure having a plurality of solder balls arranged like a plane, called a BGA (Ball Grid Array), a structure whose outside shape is close to the chip size by making the ball pitch of the BGA narrower, called a fine-pitch BGA, any another other structure have been known.
In recent years, a wafer CSP described in the 1998 August issue of “Nikkei Microdevice” p. 44-p. 71 has been available. This wafer CSP basically is a CSP comprising wiring and array-like pad manufactured in a wafer process (preprocess) before chip dicing. It is expected that the technology makes it possible to combine the wafer process and a package process (postprocess) into one for drastically reducing package costs.
The wafer CSPs are classified into those of seal resin type and those of rewiring type. The wafer CSP of the seal resin type has a structure with a surface coated with seal resin, like that of a conventional package, wherein a metal post is formed on a wiring layer on the chip surface and is surrounded by seal resin for fixture.
Generally, it is said that if a package is mounted on a printed wiring board, a stress generated because of the thermal expansion difference between the package and the printed wiring board concentrates on a metal post; however, in the wafer CSP of the seal resin type, it is considered that the stress is scattered because the metal post lengthens.
On the other hand, the wafer CSP of the rewiring type has a structure wherein rewiring is formed without using seal resin, as shown in FIG.
9
. That is, an Al electrode
52
, a wiring layer
53
, and an insulating layer
54
are deposited on the surface of a chip
51
, a metal post
55
is formed on the wiring layer
53
, and a solder bump(ball)
56
is formed on the metal post
55
. The wiring layer
53
is used as rewiring for placing the solder balls
56
like a predetermined array on the chip.
The wafer CSP of the seal resin type provides high reliability by lengthening the metal post about 100 &mgr;m and reinforcing the metal post with seal resin. However, the seal resin forming process needs to be executed with a metal mold in the postprocess and the process becomes complicated.
On the other hand, the wafer CSP of the rewiring type has the advantages that the process is comparatively simple and moreover most steps can be executed in the wafer process. However, the stress needs to be relieved for enhancing the reliability by some method.
FIG. 10
is a drawing provided by omitting the wiring layer
53
in FIG.
9
. The Al electrode
52
forms an exposed opening formed with at least one layer of barrier metal
58
between the metal post
55
and the Al electrode
52
, and the solder ball
56
is formed on the metal post
55
.
However, in
FIGS. 9 and 10
, the joint shape of the metal post
55
and the solder ball
56
substantially matches the shape of the metal post head and is a plane perpendicular to the paper plane.
On the other hand, the solder ball
56
is connected to a pattern made of Cu formed on a mounting board. Therefore, the mounting board has a thermal expansion coefficient different from that of the semiconductor device and thus a rupture stress parallel to the above-mentioned vertical plane is applied to a neck of the solder ball, cutting the neck.
Since the metal post is made of Cu, barrier metal of Ni, Au, etc., is formed on the surface of the metal post for the purpose of preventing oxidation of the surface. Therefore, adopting Au or Ni results in an increase in costs and the barrier metal is formed by plating, thus the process becomes complicated. Further, it is difficult to control the film thickness of the barrier metal, so that variations occur in adhesion of the solder balls.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a semiconductor device having good adhesion, a reduced number of steps, and high reliability wherein solder ball is prevented from causing neck-cutting.
To the end, in a first aspect of the invention, a metal material having wettability with solder is put on the inner face of a recess part of resin corresponding to a placement area of a metal post and solder is embedded in the area surrounded by the metal material.
In a second aspect of the invention, the metal post is formed via a metal film having wettability with the solder in the recess part.
In a third aspect of the invention, the embedded solder and a solder ball consist essentially of the same material and are molded in one piece.
In a fourth aspect of the invention, the solder surrounded by the metal film is made as a columnar structure.
Since the space in which the solder post is formed has the recess part, the joint face of the solder and the metal material is made up of the perpendicular side walls of the recess part and a horizontal plane perpendicular to the side walls. Therefore, the joint face of the perpendicular side walls and the solder has a strength against a neck cutting stress acting in the direction parallel to the horizontal plane. The interface where neck cutting occurs becomes the portion indicated by arrow S in
FIG. 5
; the area can be drastically reduced as compared with the semiconductor device interface in the related art and neck cutting can be suppressed.
In a fifth aspect of the invention, the metal film is a copper film and a nickel film and wherein the solder is formed via the nickel film.
In a sixth aspect of the invention, the metal film comprises a copper film, a nickel film, and a gold film deposited in order and the solder is formed via the gold film.
In a seventh aspect of the invention, the metal post is a solder area of a columnar structure formed by solder plating.
In an eighth aspect of the invention, the solder area has a bottom face formed so as to be below a depth position of a half the depth of the recess part.
According to the composition, the metal post is embedded to below the depth position of a half the depth of the recess part and the semiconductor device becomes extremely strong against a stress in a lateral direction and becomes high in adhesion.
According to a ninth aspect of the invention, there is provided a semiconductor device manufacturing method comprising the steps of:
providing a semiconductor wafer having a wiring layer connected to a metal electrode pad and consisting essentially of Cu extended on a chip surface, an insulating layer covering the chip surface containing the wiring layer, an opening made in the insulating layer on the wiring layer, and a seed layer formed on a surface containing the opening;
forming solder in the opening by a plating method with the seed layer as a plate electrode;
removing the seed layer surrounding the opening and allowing the seed layer and the solder to remain in the opening; and
fixedly securing a solder ball to the remaining area.
In a tenth aspect of the invention, the seed layer is etched by polishing the semiconductor wafer or utilizing the remaining solder as an element of a mask.
In an eleventh aspect of the invention, after the wiring layer is formed, an Si
3
N
4
film is formed, then the insulating layer is formed.
According to the composition, reaction of polyimide and Cu can be prevented and it is made possible to enhance reliability.
In a twelfth aspect of the invention, the seed layer is formed by physically cladding a thin film of Cu and further Cu is formed on the thin film of Cu by plating.
In a thirteenth aspect of the invention, the step of forming the wiring layer consisting essentially of Cu includes the step of forming a wiring layer made of Cu in an area exposed from a first opening made on the metal pad and the proximity of the area formed on an insulating
Ono Seiichi
Shinogi Hiroyuki
Takai Nobuyuki
Tokushige Ryoji
Coleman William David
Sanyo Electric Co,. Ltd.
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