Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-06
2002-10-08
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S685000, C438S649000
Reexamination Certificate
active
06461960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device, which can simplify the process and reduce the amount of consumption of silicon atoms, by forming a TiSi
2
layer by a salicide process that is used to lower a contact resistance between a junction and metal wiring.
2. Description of the Prior Art
Generally, as a semiconductor device is more highly integrated, miniaturized and more highly functional, schemes to reduce a contact resistance between a metal wiring and a junction are studied. As one option to reduce the contact resistance, there is a method in which a silicide layer is formed on the entire surface of the junction, which is performed by a salicide process. A conventional salicide process involves two steps: a process of depositing Ti and a subsequent annealing process. By the annealing process, Ti atoms and Si atoms are reacted, so that the surface of the junction is salicided to form a TiSi
2
layer. Ti used in the reaction is deposited by a physical vapor deposition (PVD) method and the annealing process employs a rapid thermal process (RTP) in order to minimize consumption of Si atoms in the junction.
Though the contact resistance can be lowered since the TiSi
2
layer is formed on the surface of the junction, the function of the junction is lowered due to consumption of Si atoms accompanied by the process of forming the TiSi
2
layer. That is, as Ti atoms and Si atoms are reacted to form the TiSi
2
layer, consumption of Si atoms is inevitable. As the number of Si atoms (which is more than about 2.3 times the number of Ti atoms in forming the TiSi
2
layer) increases, the amount of consumption of Si atoms inevitably increases. In order to minimize consumption of the Si atoms within the junction, the deposition thickness of Ti must be as thin as possible. In this case, however, a low voltage necessary for driving the device may not be obtained. Therefore, in order to solve this problem, if the thickness increases, the leakage current characteristic is degraded due to consumption of Si atoms.
These conflicting dynamics result in a limit to the manufacture of an ultra-high integration semiconductor device requiring a shallow junction. Therefore, there is a need to minimize consumption of Si atoms within the junction while the deposition thickness of Ti is increased.
SUMMARY OF THE INVENTION
A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate for forming a TiSi
2
layer, and substantially simultaneously forming the TiSi
2
layer and depositing Ti by a plasma deposition vapor method using TiCl
4
gas and H
2
gas.
A method of manufacturing a semiconductor device according to another embodiment of the disclosure is characterized in that it includes the steps of providing a semiconductor substrate in which a device separation film, a gate and a junction are formed; forming a mask insulating film on the gate and forming a gate spacer at both sidewalls of the gate; forming a silicon layer on an exposed surface of the junction; forming a TiSi
2
layer on the silicon layer and substantially simultaneously depositing Ti by a plasma deposition vapor method using TiCl
4
gas and H
2
gas; and removing the Ti layer that is unreacted after the TiSi
2
layer is formed.
In the above, the silicon layer is preferably formed by a selective epitaxial growth method using one of SiH
4
, SiH
2
Cl
2
, SiHCl
3
, and SiCl
4
as a reaction gas.
The TiSi
2
layer is formed under conditions wherein power is in the range of about 100 Watts to about 500 Watts, pressure is in the range of about 2 Torr to about 20 Torr, the temperature of the semiconductor substrate is in the range of about 400° C. to about 700° C., the TiCl
4
gas flow rate is about 10 mg/min to about 100 mg/min, and the H
2
gas flow rate is about 1000 sccm to about 3000 sccm.
REFERENCES:
patent: 5950083 (1910-09-01), Inoue et al.
patent: 5972790 (1999-10-01), Arena et al.
patent: 5976976 (1999-11-01), Doan et al.
patent: 6004872 (1999-12-01), Tezuka et al.
patent: 6140230 (2000-10-01), Li
patent: 6204170 (2001-03-01), Taguwa
patent: 6291346 (2001-09-01), Tai
Dang Trung
Marshall Gerstein & Borun
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