Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

2000-02-17

2002-01-08

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S142000, C438S299000, C438S301000, C438S305000, C438S649000, C438S658000, C438S683000, C438S721000, C438S749000, C438S075000, C257S043000, C257S757000, C257S754000, C257S768000

Reexamination Certificate

active

06337272

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device in which, in order to lower resistance of a P-type gate electrode, a P type source/drain region, an N type gate electrode and an N type source/drain region, a metal silicide layer having substantially equal sheet resistance can be formed simultaneously on each of these electrodes and regions in a self aligned manner.
BACKGROUND OF THE INVENTION
A conventional SALICIDE process, that is, a self-aligned silicide process, which is known as one of semiconductor device manufacturing methods, is disclosed in Japanese patent laid-open publication No. 8-069497. With reference to the drawings, description will be made on such conventional method of manufacturing a semiconductor device.
FIGS. 7A and 7B
and
FIGS. 8A and 8B
are illustrations, in order of process steps, of cross-sectional views of a portion of a semiconductor device substrate obtained after respective process steps according to the conventional method of manufacturing a semiconductor device.
First, as shown in
FIG. 7A
, an N type well
202
is formed at an area of a silicon wafer or silicon substrate
201
where a P channel transistor is to be formed, by using a known method, for example, an ion implantation method and the like. Then, on the surface of the silicon substrate
201
, a field oxide film
203
is formed by using a selective oxidation method. A gate insulating film
204
made of silicon oxide film and the like is then formed in an active area surrounded by the field oxide film
203
, and a polycrystalline silicon (polysilicon) film which becomes a gate electrode is formed on the gate insulating film
204
. Phosphorus is then doped into the polysilicon film by using a known method, thereby electrical resistivity of the polysilicon film is lowered. Thereafter, by using a well known photolithography method and a well known dry etching method, the polysilicon film is patterned, and the gate electrode
205
is formed as shown in FIG.
7
A.
Next, by an ion implantation method which uses the gate electrode
205
, the field oxide film
203
and a resist film formed by a photolithography method and not shown in the drawing as a mask, N type impurity diffused layers
206
having a predetermined low impurity concentration are formed in an active area of the silicon substrate
201
in which an N channel transistor is to be formed. Similarly, by an ion implantation method which uses the gate electrode
205
, the field oxide film
203
and a resist film formed by a photolithography method and not shown in the drawing as a mask, P type impurity diffused layers
207
having a predetermined low impurity concentration are formed in the N type well
202
. Thereafter, on side surfaces of the gate electrode
205
, sidewall spacers
208
made of silicon oxide films or silicon nitride films are formed by using a known CVD technology and a known etching technology.
Thereafter, by an ion implantation method which uses the gate electrode
205
, the sidewall spacers
208
, the field oxide film
203
and a resist film formed by a photolithography method and not shown in the drawing as a mask, N type source/drain regions
209
having a higher impurity concentration than that of the N type impurity diffusion layers
206
are formed in an active area of the silicon substrate
201
in which the N channel transistor is to be formed. Similarly, by an ion implantation method which uses the gate electrode
205
, the sidewall spacers
208
, the field oxide film
203
and a resist film formed by a photolithography method and not shown in the drawing as a mask, P type source/drain regions
210
having a higher impurity concentration than that of the P type impurity diffused layers
207
are formed in the N type well
202
. After the ion implantation, heat treatment process is performed if necessary. By these process steps, the N type source/drain region
209
and the P type source/drain region
210
are formed as a lightly doped drain (LDD) structure. Thereby, the structure shown in
FIG. 7A
is obtained.
It should be noted that, in the ion implantation process for forming the N type source/drain region
209
and the ion implantation process for forming the P type source/drain region
210
, the gate electrode
205
is used as a mask and impurities are also injected into the gate electrode
205
. Therefore, the gate electrode
205
on the side of the N channel transistor has N conductivity type at least at an upper portion thereof, and is called an N type gate electrode
205
a
hereafter. Also, the gate electrode
205
on the side of the P channel transistor has P conductivity type at least at an upper portion thereof, and is called a P type gate electrode
205
b
hereafter.
Then, a native oxide film not shown in the drawing and formed on the surface of the polysilicon film as the gate electrode and on the surface of the silicon substrate is removed by etching and the like. The substrate is then placed into a chamber of a magnetron sputtering apparatus not shown in the drawing. Cobalt, which is a metal having a high melting point, is deposited by sputtering on whole surface of the substrate while heating the substrate at a temperature from 200 degrees Celsius to 500 degrees Celsius, for example, at 450 degrees Celsius. Thereby, as shown in
FIG. 7B
, a cobalt film
211
is formed on the field oxide film
203
, the sidewall spacers
208
and the like. On the other hand, a cobalt film deposited on the N type gate electrode
205
a,
the P type gate electrode
205
b,
the N type source/drain region
209
and the P type source/drain region
210
chemically reacts with underlying material, that is, single crystalline silicon or polysilicon via surface reaction to form a dicobalt monosilicide (Co
2
Si) film
212
.
However, according to an analysis by the inventor of the present invention, as shown in
FIG. 7B
, it has been found that, among portions of the dicobalt monosilicide (Co
2
Si) film formed on the N type gate electrode
205
a,
the P type gate electrode
205
b,
the N type source/drain region
209
and the P type source/drain region
210
, portions of the dicobalt monosilicide in dicobalt monosilicide (Co
2
Si) film
212
a
formed on the P type gate electrode
205
b
and the P type source/drain region
210
further chemically react with silicon to produce cobalt monosilicide (CoSi). It has also been found that, on the upper portion of dicobalt monosilicide (Co
2
Si) film
212
a
formed on the P type gate electrode
205
b
and the P type source/drain region
210
, a cobalt film portion
211
a
is left unreacted.
Next, as shown in
FIG. 8A
, a rapid thermal annealing (RTA) process is performed in nitrogen atmosphere at a temperature equal to or higher than 500 degrees Celsius. Thereby, reaction of the dicobalt monosilicide (Co
2
Si) portions and cobalt monosilicide portions on the N type gate electrode
205
a,
the P type gate electrode
205
b,
the N type source/drain region
209
and the P type source/drain region
210
is further progressed and a film
213
comprising cobalt monosilicide and/or cobalt disilicide (CoSi
2
) is formed.
The cobalt film
211
existing on the field oxide film
203
and the sidewall spacers
208
becomes a film in which a part of, for example, the surface portion of, the film is oxidized. Also, according to an analysis by the inventor of the present invention, it has been found that the cobalt film portion
211
a
existing on the upper portion of the dicobalt monosilicide (Co
2
Si) film
212
a
formed on the P type gate electrode
205
b
and the P type source/drain region
210
also becomes a film in which a part of, for example, the surface portion of, the film is oxidized.
As shown in
FIG. 8B
, the substrate is then immersed in a mixed aqueous solution of hydrochloric acid and hydrogen peroxide. By such wet etching, the cobalt film portion which is left unreacted or which is partially oxidized is selec

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