Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2000-06-16
2001-10-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S162000, C438S296000, C257S336000
Reexamination Certificate
active
06309939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, in particular to a method of forming a junction region of a semiconductor device.
2. Description of the Related Prior Art
Generally, a semiconductor device has both regions of a cell region and a peripheral circuit region, in which the cell region has a high density since a plurality of devices are integrated while peripheral circuit region has a low density since some devices are disposed in spacing. Though the cell region and the peripheral circuit region have a same topology, aspect ratio of the cell region is higher than that of the peripheral circuit region. For example, when an etching process for forming a contact hole is performed, a junction region of the peripheral circuit is fully opened but a junction of the cell region is not opened due to the cell region a high integration and topology of a gate electrode.
In a conventional method, a junction region of the cell region is formed over a substrate to prevent contact defect. The conventional method will be described in conjunction with accompanying drawings.
Referring to
FIG. 1A
, field oxide layer
2
are formed on a semiconductor substrate
1
, in which a cell region C and a peripheral region P are defined, by means of a conventional method. A gate insulation layer
3
, a conductive layer
4
and a hard mask
5
are sequentially deposited on the semiconductor substrate
1
and patterned with a desired width to form gate electrodes.
Side wall spacers
6
are formed on both the side wall of the gate electrodes as shown in
FIG. 1B. A
silicon nitride layer
7
is then formed on the resulting structure alter forming the side wall spacers
6
and patterned to cover the peripheral region P.
As shown in
FIG. 1C
, doped epitaxial layers
8
are grown on the cell region C of the exposed semiconductor substrate
1
by means of a chemical vapor deposition process. Generally, the doped epitaxial layers
8
are not grown on an oxide layer and a silicon nitride layer. Hence, the doped epitaxial layers
8
are not formed on the field oxide layer
2
, the hard mask
5
, the side wall spacers
6
and the peripheral region P covered by the silicon nitride layer
7
. The doped epitaxial layers
8
are only formed on a predetermined junction regions of the cell region C. Topology between the gate electrodes and the substrate in the cell region C is reduced by forming the epitaxial layers
8
.
As shown in
FIG. 1D
, an impurity for a source and a drain is implanted into the substrate and a rapid thermal annealing is performed, thereby forming junction regions
9
a
,
9
b
,
9
c
and
9
d
. Since the peripheral region P is covered with a silicon nitride layer
7
, the junction regions
9
c
and
9
d
are formed into thin thickness. Also, the impurity existing in the epitaxial layers
8
of cell region C is diffused into the semiconductor substrate
1
by means of the rapid thermal annealing so that the junction regions
9
a
and
9
b
are formed. Substantial junction regions of the cell region C are the junction regions
9
a
and
9
b
diffused into the substrate
1
and the epitaxial layers
8
formed on the substrate
1
.
Referring to
FIG. 1E
, the silicon nitride layer
7
covering the semiconductor substrate
1
is removed by means a conventional method and an inter-insulation layer
10
is then formed on a resulting structure of the semiconductor substrate
1
.
As described above, topology between the gate electrode and the junction region is reduced since the junction region of the cell region is formed over the substrate in the form of projection. Hence, a contact hole can be formed with easy.
However, there is a problem in that a threshold voltage of PMOS transistor, which is formed in a cell region or a peripheral region, is increased due to several times rapid thermal annealing. That is, the conventional method requires a high temperature during the growth of the epitaxial layer and the thermal process to form the junction region. As a result, threshold voltage of the PMOS transistor that is sensitive to thermal is changed.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a method of manufacturing a semiconductor device that can prevent change of device characteristic by reducing the number of the thermal process.
To achieve the above object, a method of manufacturing a semiconductor device according to the present invention, comprising the steps of:
forming gate electrodes on a semiconductor substrate having a cell region and a peripheral region;
forming spacers on both side walls of the gate electrodes;
implanting impurity into the semiconductor substrate of the peripheral region;
forming a growth suppression layer on gate electrodes and surface of the semiconductor substrate in the peripheral region;
forming doped epitaxial layers over predetermined portions of the semiconductor substrate in a cell region so that the impurity implanted into the semiconductor substrate in the peripheral region is diffused in the semiconductor substrate to form junction regions and impurity existing in the doped epitaxial layers of the cell region is diffused into the semiconductor substrate; and
removing the growth suppression layer.
The growth suppression layer is formed of a silicon nitride layer having 100 to 200 Å in which the silicon nitride layer is formed by means of a low pressure chemical vapor deposition process.
It is desirable that the spacer is formed of an oxide layer when the growth suppression layer is a silicon nitride layer.
The doped epitaxial layers are formed with thickness of 500 to 1500 Å and contain phosphorous therein.
In case of forming the doped epitaxial layers by means of a low pressure chemical vapor deposition process, the doped epitaxial layers are formed by performing a baking process for 1 to 5 minutes under temperature of 800 to 900 degrees Celsius and hydrogen environment and by performing a growing process for 3 to 10 minutes in in-situ with supplying of dichlorosilane (DCS) of 30 to 300 sccm, phosphine of 50 to 300 sccm and HCl of 30 to 200 sccm under pressure of 10 to 50 torr and temperature of 750 to 950 degrees Celsius.
In case of forming the doped epitaxial layers by means of an ultra high vacuum chemical vapor deposition, a deposition gas such as silane or disilane is used and it is performed under pressure less than 1 torr and temperature of 600 to 700 degrees Celsius.
It is desirable that a cleaning process is performed between the formation of the growth suppression layer and the formation of the doped epitaxial layers to remove a native oxide layer occurred to surface of the substrate the remaining growth suppression layer of the cell region. It is desirable that the cleaning process uses RCA cleaning, UV ozone cleaning or HF dipping processes. The gate electrodes are formed by sequentially forming a gate insulation layer, a conductive layer and a hard mask, and patterning a portion of the hard mask, the conductive layer, and the gate insulation layer.
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Elms Richard
Hyundai Electronics Industries Co,. Ltd.
Luu Pho
Pennie & Edmonds LLP
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