Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-28
2001-06-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S634000, C438S638000, C438S692000, C438S700000
Reexamination Certificate
active
06251774
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device comprising a wiring element having dual damascene structure formed on a lower wiring layer.
2. Description of the Background Art
A wiring pattern of a semiconductor device is often made from a low resistance material such as copper. A multilayer wiring pattern formed from copper usually employs a dual damascene structure; that is, a structure made by forming via holes and wiring trenches in an interlayer dielectric film and then filling the via holes and the wiring trenches with metal.
FIGS. 13A
to
13
C show cross-sectional views for describing a method of manufacturing a former semiconductor device having a wiring pattern of dual damascene structure.
According to the former manufacturing method, after formation of a trench etch stopper film and a base dielectric film in predetermined locations on a silicon substrate, a lower wiring layer
10
is formed from copper illustratively, through photolithography and etching. A first silicon nitride (Si
3
N
4
) film
12
, a first silicon oxide film
14
, a second silicon nitride (Si
3
N
4
) film
16
, and a second silicon oxide film
18
are formed, in this sequence, on the lower wiring layer
10
. Further, a first photoresist film
20
is formed on the second silicon oxide film
18
in such a way as to have an opening corresponding to a via hole
19
.
A semiconductor wafer is then subjected to anisotropic dry etching for opening the via hole
19
while the first photoresist film
20
is used as a mask. The etching is carried out until the first silicon nitride film
12
becomes exposed within the via hole
19
(FIG.
13
A). During the etching, the first silicon nitride film
12
acts as an etch stopper.
After completion of the etching for the purpose of opening the via hole
19
, the first photoresist film
20
is removed from the second silicon oxide film
18
. In place of the first photoresist film
20
, a second photoresist film
22
is formed on the second silicon oxide film
18
in such a way as to have an opening corresponding to a wiring trench (FIG.
13
B).
The semiconductor wafer is subjected to anisotropic dry etching for forming a wiring trench
24
while the second photoresist film
22
is used as a mask (FIG.
13
C). This etching is carried out under conditions such that the silicon oxide film can be removed at a great etching selective ratio with respect to the silicon nitride film. At this time, the first and second silicon nitride films
12
and
16
are used as etch stopper films. The semiconductor wafer is further subjected to etching for the purpose of removing the second silicon nitride film
16
and the first silicon nitride film
12
exposed within the via hole
19
. After the etching has been performed correctly, there are formed the via hole
19
through which the surface of the lower wiring layer
10
is exposed and the wiring trench
24
which connects with the via hole
19
.
During the etching for the purpose of forming the wiring trench
24
, the first silicon nitride film
12
is constantly exposed to etchant at the bottom of the via hole
19
(the area of the silicon nitride film
12
that is exposed to etchant will be hereinafter referred to as an “exposed portion”). Because of variations in manufacturing conditions, the exposed portion may be etched in large amounts during the process of etching for the purpose of opening the via hole
19
. Under such a condition, the via hole
19
may pass through the first silicon nitride film
12
during the course of etching for opening the wiring trench
24
, thereby resulting in exposure of the surface of the lower wiring layer
10
. In this case, as shown in
FIG. 13C
, the lower wiring layer
10
will be damaged if the etching continues further even after exposure of the lower wiring layer
10
.
As mentioned above, under the former manufacturing method, the etching for the purpose of opening the wiring trench
24
is carried out after opening of the via hole
19
. In this case, the first silicon oxide film
14
and the second silicon nitride film
16
are more susceptible to etching at the vicinity of the opening end of the via hole
19
than at the remaining portions of the same. For this reason, under the former manufacturing method, the through-hole (i.e., the via hole
19
) formed in the second silicon nitride film
16
is apt to be increased in diameter during the process of etching for opening the wiring trench
24
.
FIG. 14
shows the through-hole formed in the second silicon nitride film
16
. The diameter of the through-hole is enlarged during the course of etching. In
FIG. 14
, a profile indicated by a broken line depicts an ideal shape of the through-hole, which would be obtained when the first and second silicon nitride films correctly act as stopper films. In
FIG. 14
, the lower wiring layer
10
has a width which is substantially equal to the diameter of the ideal via hole
19
, and a barrier metal layer
26
is formed around the lower wiring layer
10
.
As shown in
FIG. 14
, if the through hole of the second silicon nitride film
16
is increased in diameter during the process of formation of the wiring trench
24
, the via hole
19
is formed so as to tapers toward the bottom. If the via hole
19
is tapered, the side surface of the lower wiring layer
14
becomes more apt to be exposed to etchant. As a result, the barrier metal layer
26
is damaged under the influence of the etching, and the primary metal contained in the wiring layer is likely to be exfoliated from the barrier metal layer
26
. In this way, the former semiconductor device manufacturing method encounters a problem of the lower wiring layer
10
being subjected to various types of damage during formation of a wiring element having dual damascene structure on the lower wiring layer
10
.
Copper used as the primary metal of the wiring layer in the former semiconductor device has a higher reflectivity than that of aluminum. According to the former manufacturing method, at the time of patterning of the first photoresist film
20
for opening the via hole
19
(see
FIG. 13A
) and at the time of pattering of the second photoresist film
22
for forming the wiring trench
24
(see FIG.
13
B), the photoresist films are sensitized through exposure to light (e.g., I-lay) irradiated from above. The photoresist is sensitized by the direct light irradiated from above and reflected light that is reflected by the substrate after passage through the photoresist. Therefore, the sensitized state of the photoresist is greatly affected by interference between the direct light and the reflected light.
A silicon oxide film and a silicon nitride film used in the former semiconductor device usually permit passage of light. Therefore, some of the light that has passed through the photoresist passes through the silicon oxide film and the silicon nitride film, thus arriving at the lower wiring layer
10
and the surface of the silicon substrate. As a result, the photoresist formed above the lower wiring layer
10
receives the light reflected by the lower wiring layer
10
. The photoresist formed above the locations where the lower wiring layer
10
is not present receives the light reflected from the surface of the silicon substrate laid beneath the lower wiring layer
10
.
The optical path along which the light reflected from the lower wiring layer
10
arrives at the photoresist changes according to variations in the thickness of the interlayer dielectric film interposed between the light-reflecting surface and the photoresist. Similarly, the optical path along which the light reflected from the surface of the silicon substrate arrives at the photoresist change according to variations in the thickness of the interlayer dielectric film interposed between the light-reflecting surface and the photoresist. Further, in the event of variations in these optical paths, the state of in
Harada Akihiko
Saito Takayuki
Anya Igwe U.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
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