Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2000-08-17
2002-04-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S309000, C438S375000
Reexamination Certificate
active
06368929
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to methods of making semiconductor components and the components thereof, and more particularly to bipolar transistors.
BACKGROUND OF THE INVENTION
It is well known that bipolar transistors, especially heterojunction bipolar transistors (HBTs) based on GaAs technologies, can exhibit excessive current leakage at emitter/base contact junctions. See Lin, Hao-Hsiung et. Al., “Super-gain AlGaAs/GaAs Heterojunction Bipolar Transistors using an Emitter Edge-thinning design,” Appl. Phys. Lett. 47 (8), Oct. 15 1985, pp. 839-841. Surface recombination of electrons in the base material and the spacing between the emitter and base contacts of the devices degrade transistor performance and affect device reliability.
The prior art has attempted to minimize the parasitic capacitance at these emitter/base junction areas by, for example, producing devices
10
on a substrate
26
. An area between the emitter layer
34
and the base contacts
48
is covered with a photoresist material
50
prior to etching the device as described in U.S. Pat. No. 5,804,877 (Fuller et. al.) and illustrated in FIG.
1
. The disadvantage of this method is the use of an additional photolithography step during the device fabrication process that causes damage to collector sidewalls during the stripping of the photoresist and limits the useful operating voltage of the transistor.
To address the surface recombination problem that reduces the reliability of the HBTs, a fabrication process described in U.S. Pat. No. 5,001,534 (Lunardi et. al.) required that an emitter layer (referred to as a ledge) be left intact beneath the entire base contact and electrical contact to the base layer of the device was accomplished through the intact emitter layer. The base contact metal was diffused through the emitter layer, and the reliability of the transistors were compromised.
In U.S. Pat. No. 5,840,612 (Oki et. al.) surface passivation of HBTs was again addressed by using a depleted layer of widebandgap semiconductor (also referred to as a ledge) over the extrinsic base region of the transistor. The ledge thickness was defined by selectively etching away semiconductor layers above the widebandgap semiconductor; however, it is difficult to achieve a consistent ledge thickness and thus large variations in the device's characteristics result.
As demand for more reliable device performance continues to increase, the need for semiconductors, especially HBTs based on GaAs technologies, which exhibit maximum operating voltages has become apparent.
Accordingly, a need exists for a method of manufacturing a semiconductor component, and a semiconductor component thereof, that is both reliable and exhibits maximum operating voltages.
REFERENCES:
patent: 4839303 (1989-06-01), Tully et al.
patent: 4954457 (1990-09-01), Jambotkar
patent: 5001534 (1991-03-01), Lunardi et al.
patent: 5019524 (1991-05-01), Mitani et al.
patent: 5264379 (1993-11-01), Shikata
patent: 5272095 (1993-12-01), Enquist et al.
patent: 5448087 (1995-09-01), Streit et al.
patent: 5683919 (1997-11-01), Tserng
patent: 5702958 (1997-12-01), Liu et al.
patent: 5710068 (1998-01-01), Hill
patent: 5717231 (1998-02-01), Tserng et al.
patent: 5757039 (1998-05-01), Delaney et al.
patent: 5804877 (1998-09-01), Fuller et al.
patent: 5840612 (1998-11-01), Oki et al.
patent: 6037616 (2000-03-01), Amamiya
patent: 03236224 (1991-10-01), None
patent: 04722 (1992-01-01), None
patent: 052754444 (1993-10-01), None
patent: 2000260975 (2000-09-01), None
Wolf, S.; Silicon Processing for the VLSI Era Volume 2: Process Integration, Sunset Beach, CA, 1990, p.p. 486-488.*
H. Lin et al., “Super-gain AlGaAs/GaAs heterojunction bipolar transistors using an emitter edge-thinning design”, American Institute of Physics, Appl. Phys. Letter 47 (8), Oct. 15, 1985, pp. 839-841.
W. Lee et al., “Effect of Emitter-Base Spacing on the Current Gain of A1GaAs/GaAs Heterojunction Bipolar Transistors”, IEEE Electronic Device Letters, vol. 10, No. 5, May 1989, pp. 200-202.
Abrokwah Jonathan K.
Hill Darrell G.
Sadaka Mariam G.
Huffman A. Kate
Lattin Christopher
Motorola Inc.
Niebling John F.
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