Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2002-09-06
2004-10-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S303000, C438S304000, C438S305000, C257S331000, C257S365000, C257S366000
Reexamination Certificate
active
06806126
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, in general, to semiconductor components and, more particularly, to the gate resistance of semiconductor components.
BACKGROUND OF THE INVENTION
Semiconductor device manufacturers are constantly improving device performance while lowering their cost of manufacture. One way manufacturers have reduced costs has been to shrink the sizes of the devices so that more devices can be made from a single semiconductor wafer. However, in reducing the device sizes other factors arise that limit their performance. For example, as the semiconductor devices are made smaller or shrunk, the source-drain breakdown voltage decreases, junction capacitance increases; and the threshold voltage becomes unstable. Collectively, these adverse performance effects are referred to as short channel effects. Typical techniques for mitigating short channel effects rely on adjusting the electric field in the channel region to minimize the peak lateral electric field of the drain depletion region.
In addition to increasing device density, shrinking semiconductor device sizes decreases their gate width, which in turn reduces their channel lengths and improves transistor performance. However, as the gate width is decreased, it becomes increasingly difficult to form silicide on the gate structures. The inadequate formation of silicide results in an increase in the gate resistance. Because silicide lowers gate resistance and improves transistor performance, it is desirable to efficiently and reliably form silicide on the gate structures.
FIG. 1
is a cross-sectional side view of a portion of a prior art semiconductor component
10
during an intermediate stage of manufacture. What is shown in
FIG. 1
is a semiconductor substrate
12
having a major surface
14
. A gate structure
16
comprising a gate oxide
18
and a gate
20
having sidewalls
22
is disposed on major surface
14
. Semiconductor component
10
includes a source extension region
24
, a drain extension region
26
, a source region
28
, and a drain region
30
. Oxide spacers
32
are formed adjacent sidewalls
22
and nitride spacers
34
are formed adjacent oxide spacers
32
. Oxide spacers
32
offset the extension implants that form source and drain extension regions
24
and
26
, respectively, from gate sidewalls
22
. Nitride spacers
34
offset the deep source and drain regions
28
and
30
, respectively, from the respective source and drain extension regions
24
and
26
. A layer of refractory metal
36
is formed on gate
20
, source region
28
, and drain region
30
. As those skilled in the art are aware, silicide is formed from the portions of the source and drain regions
28
and
30
, respectively, and the portion of gate
20
that are in contact with refractory metal layer
36
. With respect to gate
20
, spacers
32
and
34
limit formation of silicide to its top surface. Because gate resistance is dependent upon the amount of gate surface area available for silicide formation, limiting the amount of available gate surface area for silicide formation limits the ability to lower the gate resistance.
Accordingly, what is needed is a semiconductor component having narrow gate widths and a method for manufacturing these semiconductor components which allows sufficient silicide formation so that the gate resistance remains low.
SUMMARY OF THE INVENTION
The present invention satisfies the foregoing need by providing a semiconductor component and a method for manufacturing the semiconductor component that provides sufficient gate silicon for silicide formation to reduce gate resistance. In accordance with one aspect, the present invention comprises a method for forming a semiconductor component in which a gate structure having first and second sides and a top surface is formed on a semiconductor material of a first conductivity type. First and second nitride spacers are formed adjacent the first and second sides of the gate structure. A first doped region and a second doped region are formed in the semiconductor material, wherein the first and second doped regions are aligned to the first and second nitride spacers. A layer of nitride is disposed over the first and second nitride spacers and the gate structure. The layer of nitride is anisotropically etched to form third and fourth nitride spacers adjacent the first and second nitride spacers, respectively. The layer of nitride is overetched to expose portions of the first and second sidewalls and the top surface of the gate structure. A third doped region and a fourth doped region are formed in the semiconductor material, wherein the third and fourth doped regions are aligned to the third and fourth spacers, respectively. Silicide is formed along portions of the first and second sides of the gate structure, on the top surface of the gate structure, and in the third and fourth doped regions.
In accordance with another aspect, the present invention includes a semiconductor component comprising a semiconductor material having a gate structure formed thereon. The gate structure has a top surface and first and second sides. A pair of spacers are adjacent the first side of the gate structure such that the spacers cover a portion of the first side of the gate structure and a pair of spacers are adjacent the second side of the gate structure such that the spacers cover a portion of the second side of the gate structure. Silicide is formed along the portions of the first and second sides of the gate structure not covered by the spacers as well as on the top surface of the gate structure. Because silicide is formed along the first and second sides of the gate structure as well as the top surface, the gate resistance is lowered.
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Kammler Thorsten
Luning Scott
Wieczorek Karsten
Advanced Micro Devices , Inc.
Dover Rennie Wm.
Drake Paul
Nelms David
Tran Mai-Huong
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