Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2000-11-13
2002-03-19
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S684000, C257S687000, C257S706000, C438S107000
Reexamination Certificate
active
06359335
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of encapsulating a semiconductor package assembly or an array of such semiconductor package assemblies typically arranged on a supporting panel, while protecting the package's exposed terminals.
BACKGROUND OF THE INVENTION
In the construction of semiconductor chip package assemblies, it has been found desirable to interpose encapsulating material between and/or around elements of the semiconductor packages in an effort to reduce and/or redistribute the strain and stress on the connectors between the semiconductor chip and a supporting circuitized substrate during operation of the chip, and to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor die and the other elements of the chip package.
It is often desirable to package a semiconductor chip assembly such that it can be handled with less fear of damage to the assembly so that a heat sink can be married with the semiconductor chip. However, if a semiconductor chip assembly is to be so packaged, the utmost care must be taken during the packaging process to avoid affecting the integrity of the terminals on the chip carrier. In particular, it is important to avoid contaminating the terminals on the chip carrier with the encapsulant.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the both disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the coefficient of thermal expansion (“CTE”) mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, it disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
In some arrangements used heretofore, the compliant layer is formed by stenciling a thermoset resin onto the chip carrier and then curing the resin. Next, additional resin is applied to the exposed surface of the cured layer, this additional resin is partially cured, and the resulting tacky adhesive surface was used to bond the elastomeric layer to the chip and the chip carrier. Once attached, the entire structure is heated and fully cured. The leads are then bonded to respective chip contacts. An encapsulant material is then disposed under and around the leads from the terminal side of the assembly. This process amounts to very carefully depositing a controlled amount of encapsulant on the periphery of the contact surface of the chip from the terminal side of the assembly, building layer upon layer of encapsulant until the leads are fully encapsulated. In such a process, the encapsulant is held in place by the surface tension of the encapsulant material between the dielectric layer and the contact bearing surface of the chip. Using such a method, the encapsulant material may creep on to the exposed surface of the dielectric layer potentially contaminating the terminals and also overcoming the surface tension of the encapsulant further causing the encapsulant to get onto other surfaces of the assembly or onto adjacent chip assemblies.
Accordingly, a method of controlling the encapsulation of a semiconductor chip package assembly such that the integrity of the terminals and leads are not affected is desirable.
SUMMARY OF THE INVENTION
The present invention provides a method of encapsulating a semiconductor device and associated package structures.
The method according to the present invention includes a method of packaging a plurality of semiconductor chips in which a compliant spacer layer is disposed between a top surface of a sheet-like substrate and surface of each semiconductor chip, wherein the semiconductor chip has contacts a surface thereof and wherein the substrate has terminals at least some of which lie outside the periphery of the chip. The substrate terminals and the chip contacts are then electrically connected to one another by flexible, electrically conductive lead. A unitary support structure is then aligned with the chips and attached to or abutted against the compliant layer around the periphery of the chips. A curable liquid encapsulant is then deposited around at least a portion of the periphery of each chip on top the unitary support structure so as to encapsulate the leads and at least one surface of the chip. Alternately, the curable liquid encapsulant may deposited around at least a portion of the periphery of each chip so as to encapsulate the leads and at least one surface of the chip and the unitary support structure may then aligned with the chips and attached to (and/or embedded in) the encapsulant around the periphery of the chips. The unitary support structure may be conductive (electrically or thermally) or insulative and further may have apertures or slots therein for reducing voids or bubbles between the unitary support structure and the encapsulant during the attached step. Optionally, a additional step of applying uniform pressure to the chip assemblies prior to the curing step may be employed such that such pressure reduces voids or bubbles between the unitary support structure and the encapsulant. The encapsulant is then cured to define an integrated composite of chip packages which may be singulated into individual chip packages or into multi-chip modules. Typically, the substrate is held taut of a frame during the packaging process.
The structures according to the present invention include a multi-chip frame assembly comprising a frame having a central aperture and a flexible substrate having electrical leads and terminals, said substrate being attached to the frame across the aperture. A plurality of chips, each having a plurality of chip contacts, are attached to the substrate such that at least some of the substrate terminals are lying outside the periphery of the chips. The chip contacts are electrically connected to respective substrate terminals. A unitary support structure having a plurality of apertures therethrough is attached to the substrate within the central aperture of the frame such that at least some of the substrate terminals underlying the unitary support structure. A compliant layer is disposed between the chip and the substrate and the unitary support structure and the substrate. The assembly of parts thereby defining an integrated composite of chip packages.
In one preferred embodiment of the present invention, the compliant spacer layer is comprised of a plurality of compliant pads which are disposed between the substrate and the chips. Such compliant pads may also be disposed around the periphery of the chips for engagement with the unitary support structure so as to facilitate planarizing the unitary support structure along the length and width of the assembly.
The unitary support structure may be a sheet-like ring element having a plurality of apertures therethrough such that the aligning step registers each aperture with a respective chip such that each chip is at least partially received within a respect aperture. In one embodiment, a sheet like thermal spreader may be attached to the exposed major surface of such a ring element type unitary support structure to create a fully enclosed unit around each chip. In another embodiment, such a ring element type unitary support structure and the frame may be integral with one another such that they can be manufactured in a single process, such as etching or stamping. In still a further embodiment, the unitary support structure may be comprised of a plurality of substantially, integral continuous cap structures having a plurality of cavities, such that the cap s
Distefano Thomas H.
Mitchell Craig
Smith John W.
Collins D. M.
Lerner David Littenberg Krumholz & Mentlik LLP
Picardat Kevin M.
Tessera Inc.
LandOfFree
Method of manufacturing a plurality of semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a plurality of semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a plurality of semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2864806