Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-02
2004-07-20
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S648000
Reexamination Certificate
active
06764945
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a fabrication technique of a semiconductor integrated circuit device, particularly to a technique effective when adapted to the connection between metallizations of a semiconductor integrated circuit device or connection between a semiconductor substrate and a metallization.
With a recent tendency to high integration of LSI, a multilayer metallization structure having metallizations and insulating films formed alternately in repetition has been adopted. Such plural metallizations or a semiconductor substrate and a metallization are connected through an electroconductive portion (plug or the like) formed in the contact hole in an interlayer insulating film.
In Japanese Patent Application Laid-Open No. Hei 11(1999)-87353, disclosed is a technique for forming an electroconductive plug by forming, in a connecting hole CH and over a copper metallization
11
, a TiN film
12
serving effectively as a barrier layer by long throw sputtering, depositing thereover a W layer, and polishing a tungsten layer
13
and the TiN layer by CMP.
In Japanese Patent Application Laid-Open No. Hei 8(1996)-181212, disclosed is a technique for forming a second metallization film in order to prevent peeling of a TiN film and improve barrier properties, which is attained by annealing a Ti film, which has been formed in a contact hole, by collimation sputtering, forming a TiN film
23
, forming thereover a reactive sputter TiN film
24
and then depositing a W film
12
by CVD.
In Japanese Patent Application Laid-Open No. Hei 10(1998)-242271, disclosed is a technique (
FIG. 4
) for securing the contact between a connecting plug and groove metallization by forming a connecting plug
45
, making a metallization groove
46
in such a way that the connecting plug
45
invades the metallization groove
46
, forming a TiN/Ti film as an underlying film
47
by LD sputtering, and forming a Cu layer
48
a
, thereby forming a groove metallization
48
.
In Japanese Patent Application Laid-Open No. Hei 6(1994)-
140359
, disclosed is a technique for forming, in a contact hole
50
and over a BPSG film
30
, a layer
40
from a sputter target
70
through a collimator
60
by chemical reactive sputtering.
In Japanese Patent Application Laid-Open No. Hei 4(1992)-207033, disclosed is a technique for attaining good filling of a via hole and planarization of a metallization layer, which comprises depositing a first electroconductive film on the bottom of the via hole by high-temperature/high-bias or high-temperature sputtering, or selective metal CVD and then depositing thereover a second electroconductive film by traditional sputtering and vapor deposition.
In Japanese Patent Application Laid-Open No. Hei 4(1992)-207033, disclosed is a technique for constituting a plug
5
from a barrier film
5
a
obtained by depositing titanium or titanium nitride by sputtering, an underlying film Sb obtained by depositing tungsten over the barrier film
5
a
by sputtering and a filling film
5
c
obtained by depositing a tungsten film by CVD for filling therewith an opening.
SUMMARY OF THE INVENTION
With a view to overcoming connection failure between metallizations or between a semiconductor substrate and a metallization, the present inventors have carried out an investigation on a technique for filling a contact hole (via hole) with an electroconductive film.
This contact hole is formed on a metallization or a semiconductor substrate and after formation of a barrier film inside of the contact hole, an electroconductive film such as tungsten (W) film is filled inside of the contact hole. This barrier film is formed to prevent the reaction between a raw material gas and metallization (such as aluminum) upon formation of the W film.
With a miniaturization tendency of a semiconductor integrated circuit device, however, a contact hole inevitably has a larger aspect ratio. Aspect ratios exceeding 3.0, for example, deteriorate the barrier properties of the barrier film on the bottom of the contact hole, thereby increasing the frequency of connection failure.
With a miniaturization of a metallization width or diameter of a contact hole, the margin between the metallization and the contact hole tends to become smaller, thereby tending to cause positional deviation (deviation of the contact hole relative to a metallization pattern). In such a case, a sub-trench (a concave of a small diameter) appears on the side walls of the metallization as will described later, causing a more difficulty in securing barrier properties.
An object of the present invention is therefore to attain a good contact between metallizations or between a substrate and a metallization.
Another object of the present invention is to heighten the reliability of a semiconductor integrated circuit device by forming a good contact between metallizations or between a substrate and a metallization and to improve the yield of the product.
The object and another object, and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Among the present inventions disclosed by the present application, typical ones will next be described simply.
(1) A method for fabricating a semiconductor integrated circuit device according to the present invention comprises depositing a first electroconductive film in a contact hole by first sputtering, depositing a second electroconductive film over the first electroconductive film by second sputtering having higher directivity than first sputtering, and depositing a third electroconductive film over the second electroconductive film.
(2) A method for fabricating a semiconductor integrated circuit device according to the present invention comprises depositing a first electroconductive film in a contact hole by long throw sputtering or ionized sputtering, depositing a second electroconductive film over the first electroconductive film by traditional sputtering, and depositing a third electroconductive film over the second electroconductive film.
(3) A semiconductor integrated circuit device according to the present invention comprises a contact hole formed in an insulating film, a first sputter film formed on the bottom and side walls of the contact hole, a second sputter film which is formed over the first sputter film on the bottom and side walls of the contact hole and has higher directivity than the first sputter film, and an electroconductive film filled inside of the contact hole.
(4) A semiconductor integrated circuit device according to the present invention comprises a contact hole formed in an insulating film, a first sputter film which is formed on the bottom and side walls of the contact hole by long throw sputtering or ionized sputtering, a second sputter film which is formed over the first sputter film on the bottom and side walls of the contact hole and has higher directivity than the first sputter film, and an electroconductive film filled inside of the contact hole.
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Dixit et al., Ion metal plasma (IMP) depositing titanium liners for 0.25/0.18 &mgr;m multilevel interconnections,IEDM, (Dec. 1996) 357.*
Tokei et al., Step coverage and continuity of an I-PVD Ta(N) barrier layer : limitations,Proc. IEEE Int. Interconnect Tech. Conf.(Jun. 2001)213.
Ashihara Hiroshi
Okutani Ken
Saito Tatsuyuki
Suzuki Hidenori
Tanaka Uitsu
Antonelli Terry Stout & Kraus LLP
Le Vu A.
Renesas Technology Corp.
Wilson Christian D.
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