Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2000-04-19
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C257S492000
Reexamination Certificate
active
06372557
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods for manufacturing MOS field effect transistors (“MOSFETs”) and the resulting transistors. This invention also relates to methods for manufacturing lateral MOSFETs and the resulting MOSFETs.
FIG. 1
illustrates in cross section a lateral DMOS MOSFET transistor
10
constructed in accordance with the prior art. Transistor
10
comprises N+ source regions
12
a
and
12
b
, a N++ drain regions
14
a
and
14
b
, N lightly doped drain region
16
a
laterally surrounding N++ drain region
14
a
, N lightly doped drain region
16
b
laterally surrounding N++ drain region
14
b
, gate insulation regions
18
a
,
18
b
, polysilicon gates
20
a
and
20
b
, and P body regions
22
a
and
22
b
, all formed in a P- epitaxial layer
24
, which in turn is formed on a P++ substrate
26
. (The structure shown in
FIG. 1
is a small region of a much larger transistor. Gates
20
are all electrically coupled together to form one gate region. Similarly, drain regions
14
are electrically coupled together to form one drain region. Body regions
22
are electrically coupled together and to ground through P++ sinker region
28
, substrate
26
and metalization
30
, discussed below. Source regions
12
are coupled together and to ground through metalization
32
, P++ sinker region
28
, substrate
26
and metalization
30
.)
As is well known in the art, one controls the amount of current permitted to flow between drain
14
and source
12
by controlling the voltage applied to gate
20
. When a high voltage is applied to gate
20
, a conductive channel (i.e. an inversion region) forms in a portion of body region
22
underneath gate
20
, and current is permitted to flow from drain
14
to source
12
. (Actually, for the case of N transistor
10
, this current is conducted in the form of electrons flowing from source
12
to drain
14
.)
P++ sinker
28
, formed in epitaxial layer
24
, is used to electrically connect P body region
22
to P++ substrate
26
. Gold metalization
30
is used to couple substrate
26
to a reference voltage, e.g. ground. In this way, body region
22
is grounded during use. Body region
22
is connected to N+ source regions
12
via metalization
32
applied to the top surface of transistor
10
. In this way, source region
12
is also grounded during use.
Drain region
14
is electrically contacted by metalization
34
.
Transistor
10
has the following disadvantages.
1. P body region
22
is coupled to substrate
26
via P++ sinker
28
, which is formed by an implantation step followed by thermal drive in. During thermal drive in, sinker
28
laterally expands to take up a large area, e.g. to a width W of about 12.0 &mgr;m. Thus, a large amount of transistor surface area is wasted to accommodate sinker
28
.
2. Source region
12
and P body
22
are grounded via sinker region
28
. Unfortunately, there is a substantial resistance exhibited by sinker region
28
. This resistance can waste power when current flows therethrough. This resistance contributes to higher saturation voltage in the transistor, lowering efficiency and linearity of an RF amplifier comprising the transistor. It would be desirable to minimize this resistance.
SUMMARY
A method for making a transistor in accordance with one embodiment of the invention comprises:
a) forming a first doped region of a first conductivity type in a semiconductor substrate of the first conductivity type;
b) forming an epitaxial layer on the substrate;
c) forming a second doped region of the first conductivity type in the epitaxial layer;
d) performing one or more diffusion steps so that the first and second doped regions converge and electrically contact one another;
e) forming a body region in the epitaxial layer that meets and electrically contacts the second doped region;
f) forming source and drain regions in the epitaxial layer;
g) forming a gate insulation layer over at least a portion of the body region that separates the source and drain; and
h) forming a gate over the gate insulation layer.
Because of the manner in which the body region is electrically connected to the substrate (i.e. using the second doped region, which serves as a “sinker” region extending downward from the top of the epitaxial layer, and the first doped region, which serves as a “riser” region extending upward from the substrate) a transistor formed in accordance with the invention can be formed in a smaller surface area than the prior art transistor of FIG.
1
. This is because the sinker region of the present invention does not have to be as wide as that of FIG.
1
. Further, because the electrical path from the body region to the substrate does not depend entirely on dopants introduced from the top surface of the epitaxial layer, the electrical path of the present invention can be formed such that it exhibits less resistance than the corresponding electrical path through sinker region
28
of FIG.
1
.
REFERENCES:
patent: 4738936 (1988-04-01), Rice
patent: 4877749 (1989-10-01), Quigg
patent: 5146298 (1992-09-01), Eklund
patent: 5155563 (1992-10-01), Davies et al.
patent: 5374843 (1994-12-01), Williams et al.
patent: 5751054 (1998-05-01), Yimaz et al.
patent: 5869875 (1999-02-01), Hebert
patent: 5949104 (1999-09-01), D'Anna et al.
Nelms David
Polyfet RF Devices, Inc.
Vu David
LandOfFree
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