Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-06-29
2001-02-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S257000, C438S587000, 43
Reexamination Certificate
active
06184113
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a gate electrode or word line in a highly integrated and high speed semiconductor device such as 1 giga bit or more DRAM.
Presently, the gate electrode of a semiconductor device is typically composed of a doped polysilicon only or a polycide including a doped polysilicon film and a tungsten silicide (WSi
x
) sequentially deposited for reducing a resistivity thereof. However, the resistivity of tungsten silicide film is about 100 &mgr;&OHgr;•cm, so that it is still too high to be used in a 1 giga bit or more DRAM that generally requires a submicron technology (e.g. 0.18 &mgr;m or below linewidth fabrication technology). For example, in a MOS device, when the delay of an interconnect path is bigger than that of gate switching the device malfunctions. Accordingly, for the formation of a highly integrated and high performance of device, the resistivity of interconnect path (e.g. the interconnect path between the word line and the bit line in a DRAM) should be reduced as lower as possible. Therefore, the study related to a tungsten gate electrode (or word line) of 10 &mgr;&OHgr;•cm in resistivity has been continuously made.
In conventional methods of the formation of a tungsten gate electrode, a tungsten film or a polysilicon/tungsten film is deposited on a gate oxide and then selectively etched, using a gate electrode photoresist pattern to form a gate electrode. However, this conventional method has a disadvantage that the patterning for the gate electrode gives an attack to the gate oxide. Though the damage of the gate oxide can be recovered by re-oxidation process that is made for preventing the deterioration of the gate oxide and protecting the underlying semiconductor substrate during an ion implantation of LDD source/drain formation to be performed later, it causes another problems. That is, the re-oxidation makes a tungsten oxide film on the surface of gate electrode so that the overall resistivity of the gate electrode is rather increased and it destroys the gate (or word line) profile.
Also the boundary of the tungsten film and the gate oxide is so unstable that a separate glue layer may be required between the tungsten film and the gate oxide. However, since the glue layer is generally composed of the high resistivity of materials, the overall resistivity of the gate electrode is increased.
In addition, when the tungsten electrode is deposited by CVD (chemical vapor deposition) the fluorine element of source gas WF
6
attacks the gate oxide.
SUMMARY OF THE INVENTION
The present invention is devised in order to solve the problems as described above, in the conventional technology.
The object of the present invention is to provide a method of fabricating a metal (especially tungsten) gate electrode that does not require a separate glue layer as described in the conventional art.
Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of increasing the stability of the boundary between a tungsten film and a gate oxide film and preventing the gate oxide from being damaged by fluorine during the tungsten deposition.
Still another object of the present invention is to provide a method for manufacturing a semiconductor device capable of radically preventing a tungsten oxide film from being undesirably formed by re-oxidation process after gate electrode patterning.
In accordance with one embodiment of the present invention for achieving the above objects, there is provided a method for manufacturing a semiconductor device comprising the steps of: forming a gate insulating film on a semiconductor device; forming a sacrifice polysilicon film on the gate insulating film; patterning the sacrifice polysilicon film to form a sacrifice polysilicon pattern; forming a first interlayer insulating film, wherein the first interlayer insulating film does not cover the surface of the sacrifice polysilicon pattern; etching the exposed sacrifice polysilicon pattern using the first interlayer insulating film as etch mask, resulting in reserving a predetermined thickness of sacrifice polysilicon pattern; and selectively forming a metal film on the reserved sacrifice polysilicon pattern, wherein the reserved sacrifice polysilicon pattern is mostly consumed while a metal film is formed. The method may further comprise the step of performing a cleaning process after the step of etching the exposed sacrifice polysilicon pattern, the step of performing a re-oxidation process after the step of patterning the sacrifice polysilicon film, or the step of forming insulating spacers at the vertical sides of the sacrifice polysilicon pattern prior to the step of forming the first interlayer insulating film. The metal film may be composed of tungsten and wherein the step of selectively forming a metal film may comprise a first tungsten deposition step of depositing a first tungsten film using WF
6
on the sacrifice polysilicon pattern; and a second tungsten deposition step of depositing a second tungsten film on the first tungsten film using SiH
4
or H
2
along with WF
6
.
The step of forming the first interlayer insulating film may comprise the steps of: forming a first blanket interlayer insulating film; and etching in blanket the first blanket interlayer insulating film so as to expose the surface of the sacrifice polysilicon pattern. The step of forming the first blanket interlayer insulating film may comprise the steps of: depositing a silicon nitride film in blanket; and depositing a silicon oxide film in blanket on the silicon nitride film. The sacrifice polysilicon film is preferably a conductive doped film and the thickness of the reserved sacrifice polysilicon pattern after forming the metal film is preferably below 50 Å. Here, the thickness of the reserved sacrifice polysilicon pattern can be controlled to be 30 Å~300 Å after etching the exposed sacrifice polysilicon pattern.
Also, the method may further comprise the step of forming a second interlayer insulating film covering the first interlayer insulating film and the metal film. The step of forming a second interlayer insulating film comprises the steps of: depositing a silicon nitride film in blanket; and depositing a silicon oxide film on the silicon nitride film in blanket.
In summary, after a gate insulating film is formed on a semiconductor substrate, a predetermined thickness of sacrifice polysilicon film is deposited on the gate insulating film and the sacrifice polysilicon film is patterned, using a gate mask. Then a re-oxidation process can be performed and then insulating spacers are formed on the vertical sides of the sacrifice polysilicon pattern. Subsequently, a first interlayer insulating film is blanket-deposited on the overall surface of the semiconductor structure and then the first interlayer insulating film is etched by etchback or CMP (chemical mechanical polishing) to expose the sacrifice polysilicon pattern. Then, the exposed sacrifice polysilicon pattern is etched to form a recessed portion in which a predetermined thickness of sacrifice polysilicon pattern remains. Thus, the bottom of the recessed portion is the surface of the sacrifice polysilicon pattern. Only on the exposed remnant sacrifice polysilicon pattern, a metal film is deposited, in which the sacrifice polysilicon pattern located under the metal film is consumed for the reduction of WF
6
to W during the tungsten deposition. As a result, the tungsten film comes in direct contact with the gate insulating film so that a tungsten gate electrode is obtained.
The present invention as described above has advantages as follows. First, it can prevent the generation of pattern defects due to the oxidation of metal electrode by performing a re-oxidation process prior to the metal (or tungsten) deposition. Also, a thin sacrifice polysilicon pattern is used as a glue layer for metal film, a preventive film and a sacrifice film so that the boundary stability of the gate insulating film and the metal film is
Lee Sang Hyeob
Seo Hwan Seok
Blakely & Sokoloff, Taylor & Zafman
Dang Phuc T.
Hyundai Electronics Industries Co,. Ltd.
Nelms David
LandOfFree
Method of manufacturing a gate electrode in a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a gate electrode in a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a gate electrode in a semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2606661