Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-05-23
2006-05-23
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S338000, C257S350000, C257S351000, C257S357000, C257S371000, C257S381000, C257S390000, C257S412000, C257S413000
Reexamination Certificate
active
07049665
ABSTRACT:
In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline silicon layer with one mask, a gate electrode has a high melting point metal/metallic nitride barrier/polycrystalline silicon structure. The boron is pre-doped in the polycrystalline silicon layer. The phosphorus or arsenic is doped in an n-channel area. Then, the annealing in a hydrogen atmosphere with vapor added therein is performed. As a result, the boron is segregated on the interface of the metallic nitride film and the phosphorus is segregated on the interface of the gate oxide film, for forming an n+ gate.
REFERENCES:
patent: 4420344 (1983-12-01), Davies et al.
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5278441 (1994-01-01), Kang et al.
patent: 5656519 (1997-08-01), Mogami
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5683920 (1997-11-01), Lee
patent: 5780330 (1998-07-01), Choi
patent: 5831320 (1998-11-01), Kwon et al.
patent: 5882965 (1999-03-01), Schwalke et al.
patent: 5888588 (1999-03-01), Nagabushnam et al.
patent: 5942781 (1999-08-01), Burr et al.
patent: 5960289 (1999-09-01), Tsui et al.
patent: 5963799 (1999-10-01), Wu
patent: 6087225 (2000-07-01), Bronner et al.
patent: 6300184 (2001-10-01), Choi et al.
patent: 6355962 (2002-03-01), Liang et al.
patent: 6399432 (2002-06-01), Zheng et al.
patent: 6468872 (2002-10-01), Yang
patent: 6503788 (2003-01-01), Yamamoto
patent: 6593654 (2003-07-01), Oyamatsu
patent: 2002/0110969 (2002-08-01), Mori et al.
IEEE Electron Device Let., vol. 17, No. 11, Nov. 1996, pp. 497-499.
Antonelli, Terry Stout and Kraus, LLP.
Hitachi , Ltd.
Soward Ida M.
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