Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-06-28
2004-11-16
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000, C438S784000, C438S787000
Reexamination Certificate
active
06818558
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to dielectrics for field effect semiconductor devices, and more particularly to dielectrics that may retain charge for nonvolatile insulated gate field effect transistors.
BACKGROUND OF THE INVENTION
As is well known, semiconductor devices can include insulated gate field effect transistor (IGFET) type devices. IGFET-type devices typically include a transistor gate separated from a channel region by a dielectric. A potential applied to a gate can then be varied to alter channel conductivity.
While many IGFET type devices are volatile (e.g., conventional metal-oxide-semiconductor FETs), nonvolatile devices may also include IGFET-like approaches. Nonvolatile IGFET-like devices typically retain electric charge through one or more methods (e.g., storing, trapping charge). One conventional nonvolatile device can be a floating gate electrically erasable programmable read only memory (EEPROM). A floating gate EEPROM can include a floating gate electrode situated between a control gate and a channel. Charge, including electrons and/or “holes”, may be stored in a floating gate electrode. Such a charge may alter a threshold voltage of a resulting nonvolatile IGFET-type device. As will be noted below, a drawback to any floating gate device can be higher programming and/or erase voltages with respect to other nonvolatile approaches.
Another nonvolatile IGFET type device can include a dielectric interface to trap charge. For example, devices have been proposed that include a metal gate formed over a dielectric of silicon nitride and silicon dioxide. Such devices have been referred to as metal-nitride-oxide-semiconductor (MNOS) devices. A drawback to many MNOS devices has been lack of charge retention and/or uniformity of programming.
A third type of nonvolatile device may include one or more dielectric layers for storing charge. Such devices may be referred to generally as silicon-oxide-nitride-oxide-silicon (SONOS) type devices. One very basic type of SONOS device may include a polycrystalline silicon (“polysilicon”) gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon dioxide layers.
SONOS devices can have lower programming voltages than other conventional nonvolatile devices, such as some types of floating gate devices. In addition, the SONOS fabrication process can be compatible with standard complementary metal oxide semiconductor (CMOS) process technology. To maintain this compatibility, SONOS devices may be scaled along with other transistors used in the process. The ability of SONOS devices to maintain performance and reliability as they are scaled can be an important feature.
To better understand the formation of SONOS devices, a conventional way of forming a SONOS device is set forth in
FIGS. 9A
,
9
B, and
10
A to
10
F.
FIG. 9A
is a flowchart illustrating certain process steps involved in crating an integrated circuit containing SONOS devices.
FIG. 9B
is a side cross sectional view of a SONOS type device during a program operation.
FIGS. 10A-10F
set forth a number of side cross-sectional views of a portion of an integrated circuit containing SONOS devices following the various conventional process steps described in FIG.
9
A.
The conventional process described in
FIG. 9A
is designated by the general reference character
900
. A conventional process
900
may include the steps of growing a tunnel oxide (step
902
) in a furnace. Subsequently, wafers that now include the tunnel oxide can be transferred from a furnace to a different machine for growing other layers in an ONO dielectric for a SONOS-type device. In
FIG. 9A
, such a step may include transferring wafers to a chemical vapor deposition (CVD) machine (step
904
).
A conventional method
900
may further include depositing a silicon nitride layer over tunnel oxide in a CVD machine (step
906
), depositing a top oxide layer over a nitride layer in the same or a different CVD machine (step
908
), and depositing a polysilicon gate layer (step
910
).
The above steps may form various layers for a SONOS-type device. Such layers can then be patterned to form a SONOS-type transistor. Patterning steps may include forming a gate mask (step
912
), etching gate structures (step
914
), and depositing and etching a spacer layer (step
916
).
Referring to
FIG. 10A
, a side cross-sectional view of a portion of an integrated circuit prior to the beginning of a conventional process
900
is shown. An integrated circuit portion includes a substrate
1000
, and may include isolation regions
1002
formed by prior process steps. As an example, isolation regions
1002
may be formed by various conventional isolation processes including but not limited to shallow trench isolation (STI) or the local oxidation of silicon (LOCOS).
It is noted that a substrate
1000
may also include various impurity regions, formed by ion implantation and/or other diffusion methods. As but a few examples, n-type wells may be formed in a p-type substrate (or vice versa), or p-type wells may be formed within n-type wells (or vice versa).
Referring again to
FIG. 9A
, a conventional process
900
may begin by growing a tunnel oxide (step
902
) in a furnace. A portion of an integrated circuit following step
902
is set forth in FIG.
10
A. Referring to
FIG. 10A
, a portion of an integrated circuit includes a tunnel oxide
1004
on a substrate
1000
.
A conventional process
900
can continue by transferring a wafer from a furnace to a chemical vapor deposition (CVD) machine (step
904
). A conventional process
900
can continue by depositing a silicon nitride layer in a CVD machine (step
906
). A portion of an integrated circuit following step
906
is set forth in FIG.
10
B. Referring to
FIG. 10B
, an integrated circuit may now be situated within a CVD machine, an integrated circuit portion can now include a nitride layer
1006
deposited over a tunnel oxide
1004
. A nitride layer
1006
can conventionally include essentially only silicon nitride (Si
3
N
4
).
A conventional process
900
can continue by depositing a top oxide layer (step
908
) in a chemical vapor deposition (CVD) machine. Referring to
FIG. 10C
, an example of a portion of an integrated circuit following step
908
is set forth. At this point, a tunnel oxide
1004
, a nitride layer
1006
and a top oxide layer
1008
have been formed over a substrate
1000
. A top oxide layer
1008
can be conventionally formed by chemical vapor deposition (CVD).
A conventional process
900
can continue by depositing a polysilicon gate layer (step
910
). An example of a portion of an integrated circuit following a step
910
is set forth in FIG.
10
D. Referring to
FIG. 10D
, a polysilicon gate layer
1010
has been deposited on a top oxide layer
1008
. As also shown in
FIG. 10D
, a gate protection insulator
1012
may also be formed over polysilicon gate layer
1010
.
At this point, in a conventional process
900
, silicon-oxide-nitride-oxide-silicon (SONOS) layers can correspond to a substrate
1000
, tunnel oxide
1004
, nitride layer
1006
, top oxide layer
1008
, and polysilicon gate layer
1010
, respectively.
A conventional process
900
may continue with lithography and etch steps to isolate and form SONOS devices. In conventional lithography, a gate mask may first be formed (step
912
). An example of a portion of an integrated circuit following step
912
is set forth in
FIG. 10E. A
gate mask material
1014
can be deposited and patterned using any of various lithographic techniques. A gate mask material
1014
may generally include of a photoresist material.
Following the formation of a gate mask (step
912
), gate structures can be etched (step
914
). Referring now to
FIG. 10F
, a portion of an integrated circuit following step
912
is set forth. A suitable etching process can remove portions of the tunnel oxide
1004
, nitride layer
1006
, top oxide layer
1008
, polysilicon gate layer
1010
, and a gate protection insulator
1012
that are not covered by gate mas
Jenne Fred
Lancaster Loren
Ramkumar Krishnaswamy
Rathor Manuj
Cypress Semiconductor Corporation
Lebentritt Michael
Sako Bradley T.
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