Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-27
2003-09-02
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06613683
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a contact hole of a semiconductor device, and more particularly, the present invention relates to a method of manufacturing a contact hole of a semiconductor device in which an entire etching process can be advantageously controlled by setting a first etch point according to a CN (carbon—nitrogen) emission spectrum originated from a spacer during the etching process.
2. Description of the Related Art
In initially developed VLSI (very large scale integration) devices, polysilicon gates were typically adopted due to their favorable electrical characteristics, reliability, integration degree and the like.
Since polysilicon is a material having a high melting point, a self-align method can be applied in which source and drain diffusion regions are simultaneously formed during the manufacture of the gate electrode. In addition, polysilicon can be thermally oxidized after being patterned as the polysilicon gate electrode. Accordingly, damage generated at the edge portions of the gate electrodes by a reactive ion etching can be contained, and device reliability can be increased by relaxing the high fringe electric field at the edge portions when an electric potential is applied to the gate electrode.
However, for devices having a polysilicon gate and a design rule of 1 &mgr;m or less, an increased operational speed for the device which typically results from integration is eliminated. In addition, a problem of retarding signal transfer occurs due to an increase in a wire resistance of the minute device and an increase in capacitance through a reduction of a wiring pitch. Further, since polysilicon has a relatively large resistance when compared with other conductive materials, a frequency characteristic of the device is deteriorated.
Therefore, silicide compounds having a high melting point have recently been utilized as a gate electrode material. The silicide compounds have characteristics similar to polysilicon and have a lower resistance by one-tenth or less. Typically, tungsten silicide is utilized as the silicide compound.
Recently developed high-integrated semiconductor devices have a design rule as small as about 0.15 &mgr;m. Accordingly, the size of a contact hole, which is an electric contacting portion with silicon, has been gradually reduced, and the BC processing margin for an interconnection of a storage node with source/drain regions of a transistor has been further limited.
Presently, a self-align method is utilized for confirming the BC processing margin and a spacer is formed at side surfaces of a gate electrode for preventing a connection of the gate electrode with the storage node. However, confirmation of the BC processing margin is still a serious problem. Likewise, it is important to confirm the thickness of the spacer formed on the side surface of the gate electrode, that is, the shoulder margin.
FIGS. 1A through 1E
are cross-sectional views for explaining a conventional method of manufacturing a contact hole of a semiconductor device.
Referring to
FIG. 1A
, a first oxide layer
120
is formed by a local oxidation of silicon (LOCOS) method on an active region on a semiconductor substrate
100
. The active region is defined between field regions, which in turn are defined by field oxide layers
110
having a thickness of about 1800-2000 Å. Then, a first conductive layer
130
is formed on the first oxide layer
120
by depositing a conductive material to a thickness of about 800-1200 Å. The conductive material of the first conductive layer
130
may be formed of an impurity-doped conductive polysilicon.
Next, a second conductive layer
140
is formed on the first conductive layer
130
. The second conductive layer
140
is formed by depositing a metal-silicide such as tungsten silicide (WSi
x
), tantalum suicide (TaSi
2
), molybdenum silicide (MoSi
2
), etc. to a thickness of about 1300-1700 Å.
A first insulating layer
150
is formed on the second conductive layer
140
. The first insulating layer
150
is formed by depositing a nitride compound such as silicon nitride (SiN) to a predetermined thickness by a plasma enhanced chemical vapor deposition method. The first insulating layer
150
passivates (protects) the second conductive layer
140
during an etching process and an ion implantation process implemented afterward.
Then, a second oxide layer
160
is formed on the first insulating layer
150
. The second oxide layer
160
is formed by depositing a hot temperature oxide (HTO) such as silicon oxide to a predetermined thickness by a low pressure chemical vapor deposition method. The second oxide layer
160
functions as an etching stopper during an etching process implemented afterward.
Referring to
FIG. 1B
, a photoresist pattern is formed by coating photoresist on the second oxide layer
160
to form a photoresist layer (not shown) and then by patterning the photoresist using photolithography techniques. The photoresist pattern (not shown) is used to define later-formed gate electrodes.
Then, the second oxide layer
160
, the first insulating layer
150
, the second conductive layer
140
, the first conductive layer
130
and the first oxide layer
120
are subsequently and anisotropically etched by utilizing the photoresist pattern as an etching mask to form a gate electrode
170
. The gate electrode
170
include a gate oxide layer
122
, a first conductive pattern
132
, a second conductive pattern
142
, a first insulating layer pattern
152
and a second oxide layer pattern
162
.
Referring to
FIG. 1C
, a second insulating layer (not shown) is formed on the semiconductor substrate
100
(on which the gate electrode
170
is formed) by depositing silicon nitride. Then, an etch back process is implemented until the active region of the semiconductor substrate
100
is exposed to thereby form spacers
180
on the side of the gate electrode
170
. At this time, the second oxide layer pattern
162
formed from the high temperature oxide functions as an etching stopper during the etch back of the second insulating layer.
Next, an ion implantation process is implemented to implant impurities into the exposed active region of the semiconductor substrate
100
to form a diffusion region
112
of a source/drain region of a transistor. During the ion implantation process, the spacers
180
formed on both side portions of the gate electrode
170
function as a mask.
Referring to
FIG. 1D
, a dielectric interlayer
190
is formed on the semiconductor substrate
100
on which the gate electrode
170
and the spacers
180
are formed. The dielectric interlayer
190
is formed by depositing silicon oxide, BPSG, PSG, or the like, using a low pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method. Subsequently, a photoresist pattern
200
is formed by coating photoresist on the dielectric interlayer
190
and by patterning the photoresist using conventional photolithography techniques. The photoresist pattern
200
defines contact holes to be formed later.
Referring to
FIG. 1E
, the dielectric interlayer
190
is etched by utilizing the photoresist pattern
200
as an etching mask to expose the source/drain region
112
on the semiconductor substrate
100
, thereby forming a contact hole
210
and a dielectric interlayer pattern
192
. The etching of the dielectric interlayer layer is implemented using etching equipment having a high ionization degree such as ICP, TCP, SWP, DRM, etc., and by utilizing a mixture gas having a high ratio of carbon/fluorine such as C
3
F
8
, C
4
F
8
, CO, etc.
Then, a conductive material is deposited onto the substrate
100
(on which the dielectric interlayer pattern
192
including the contact hole
210
is formed) to form a contact or a storage node (not shown).
The above-described method of forming a contact hole suffers a drawback as will be explained below with reference to FIG.
2
.
In order to manufacture a semiconductor device, various layers of
Hwangbo Young
Kim Dong-Yun
Lee Hyuck-Jun
Samsung Electronics Co,. Ltd.
Vinh Lan
Volentine & Francos, PLLC
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