Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Involving nuclear transmutation doping
Reexamination Certificate
2001-04-10
2002-10-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Involving nuclear transmutation doping
C438S530000, C438S495000, C438S795000, C438S916000
Reexamination Certificate
active
06465333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and an apparatus for manufacturing a circuit by activating an impurity doped in a silicon substrate according to an annealing process.
2. Description of the Related Art
MOS (Metal Oxide Semiconductor) transistors that are used in logic circuits in recent years have a LDD (Lightly Doped Drain-source) region added inwardly of an ordinary source/drain region for suppressing the generation of a hot carrier and preventing the breakdown voltage from being lowered.
Since, however, the power supply voltage of present MOS transistors is lowered, the above aims are less important in those MOS transistors. It has been attempted to increase the concentration of the impurity in the LDD region to lower the resistance thereof. Such a region is referred to as an extension region, which is lower in concentration than the ordinary source/drain region but higher in concentration and shallower than the conventional LDD region.
One conventional MOS transistor
10
of the above structure will be described below with reference to FIG.
1
of the accompanying drawings. Conventional MOS transistor
10
is of the p type and has gate insulating film
12
and p-type gate electrode
13
that are successively deposited in a given pattern on the surface of n-type silicon substrate
11
, with side walls
14
being disposed on both sides of gate insulating film
12
and p-type gate electrode
13
.
A pair of p-type source/drain regions
15
is disposed in a surface layer of silicon substrate
11
outwardly of side walls
14
. A pair of p-type extension regions
16
with one channel region
17
interposed therebetween is disposed in a surface layer of silicon substrate
11
inwardly of p-type source/drain regions
15
.
With MOS transistor
10
of the above structure, because p-type extension regions
16
are disposed inwardly of p-type source/drain regions
15
, it is possible to suppress the generation of a hot carrier and prevent the breakdown voltage from being lowered, as is the case with the conventional LDD structure. Nevertheless, MOS transistor
10
is lower in resistance than the conventional LDD structure.
In MOS transistor
10
, gate insulating film
12
is formed as a thermally oxidized film of silicon substrate
11
. In order to allow gate insulating film
12
to function as a p channel, a p-type impurity such as boron is introduced in source/drain regions
15
, extension regions
16
, and gate electrode
13
.
A process of manufacturing such MOS transistor
10
will briefly be described below. First, the surface of silicon substrate
11
is heat-treated to form a thermally oxidized film on its entire surface, and gate electrode
13
is formed in a given pattern on the surface of the thermally oxidized film.
Using gate electrode
13
as a mask, the thermally oxidized film is subjected to a dry etching process. In the dry etching process, the thermally oxidized film is removed from the surface of silicon substrate
11
which is not masked by gate electrode
13
, producing gate insulating film
12
of the thermally oxidized film that remains unremoved beneath gate electrode
13
, as shown in
FIG. 2A
of the accompanying drawings.
Then, as shown in
FIG. 2B
of the accompanying drawings, using gate electrode
13
as a mask, the surface layer of silicon substrate
11
is lightly doped with a p-type impurity in the position of extension regions
16
. As shown in
FIG. 2C
of the accompanying drawings, side walls
14
are deposited on both sides of gate insulating film
12
and gate electrode
12
on the surface of silicon substrate
11
with the impurity injected therein by ion implantation.
Thereafter, as shown in
FIG. 2D
of the accompanying drawings, using side walls
14
as a mask, the surface layer of silicon substrate
11
is deeply doped with a p-type impurity in the position of source/drain region
15
. The impurity injected by ion implantation in silicon substrate
11
is activated by an annealing process, thereby forming source/drain region
15
and extension regions
16
. In this manner, p-type MOS transistor
10
is completed as shown in FIG.
1
.
For annealing silicon substrate
10
to form source/drain region
15
and extension regions
16
, an RTA (Rapid Thermal Annealing) process is generally used at present. According to the RTA process, as shown in
FIG. 3A
of the accompanying drawings, silicon substrate
11
placed in the atmosphere of an annealing gas of nitrogen and argon is increased in temperature to an annealing temperature of about 1000° C. at a maximum rate of the fabrication apparatus and then lowered in temperature to normal temperature at the maximum rate.
Since the temperature of silicon substrate
11
is increased and lowered at the maximum rate and directly changes from the temperature increasing mode to the temperature lowering mode according to a spike annealing pattern, the impurity in extension regions
16
is prevented from being unduly diffused, and their junction to silicon substrate
11
can be made shallow and low in resistance.
For annealing silicon substrate
10
to form source/drain region
15
and extension regions
16
, a soak annealing pattern may be employed to keep the assembly at the annealing temperature for a certain period of time, as shown in
FIG. 3B
of the accompanying drawings. The soak annealing pattern requires more processing time than the spike annealing pattern, but has an annealing temperature which may not be as high as the annealing temperature of the spike annealing pattern.
According to another process of manufacturing such MOS transistor
10
, as shown in
FIGS. 4A through 4F
of the accompanying drawings, using side walls
14
as a mask, silicon substrate
11
is deeply doped with a p-type impurity at the position of source/drain region
15
and then annealed. After side walls
14
are removed, using gate electrode
13
as a mask, silicon substrate
11
is lightly doped with a p-type impurity at the position of extension regions
16
. Side walls
14
are then deposited again, and the assembly is annealed again.
The first annealing process for activating source/drain region
15
is a normal annealing process carried out for a long period of time, rather than the RTA process. Therefore, defects due to the ion implantation are well recovered. However, inasmuch as the second annealing process for activating extension regions
16
is the RTA process, the junction of extension regions
16
may be made shallow and low in resistance.
When an n-channel MOS transistor is produced together with above p-channel MOS transistor
10
to fabricate a CMOS (Complementary MOS) transistor, the productivity is high if the p- and n-type impurities can be activated in one annealing process.
In the annealing process, the n-type impurity tends to volatilize from silicon substrate
11
, and the p-type impurity is liable to be diffused into silicon substrate
11
. When the p- and n-type impurities injected into one silicon substrate
11
by ion implantation are simultaneously activated by the annealing process, if the surface of silicon substrate
11
has not been covered with a covering film such as an oxide film, then it is preferable to add a trace of oxygen in the atmosphere thereby to form an oxide film at the same time the assembly is annealed, thus preventing the n-type impurity from being volatilized.
With the oxide film being formed at the same time the assembly is annealed, however, the p-type impurity is also diffused into the oxide film, and hence the concentration of the p-type impurity is lowered. Since the p-type impurity of boron can easily be oxidized, the oxidization promotes its diffusion, increasing the depth of the junction.
In order to solve the above problems, the applicant has proposed a method of manufacturing a circuit in Japanese laid-open patent publication No. 2000-114197. According to the proposed method, a minimum trace of oxygen is added in the atmosphere whose temperature is increasing in an RTA process in which the diffusion of
Anya Igwe U.
NEC Corporation
Sughrue & Mion, PLLC
LandOfFree
Method of manufacturing a circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2976430