Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-06-08
2003-08-26
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000
Reexamination Certificate
active
06610603
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P2000-172381 filed Jun. 8, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device for forming a capacitance element on a semiconductor substrate.
2. Description of Related Art
Conventionally, as a semiconductor device having a capacitance element, one having a structure such that first and second wiring layers formed on a semiconductor substrate serve as a lower portion electrode and an upper portion electrode, respectively, and a dielectric film formed as an intermediate layer between the wiring layers serves as a capacitance element has been known.
FIG. 5
is a diagrammatic cross-sectional view illustrating the layer structure of such a conventional semiconductor device.
In this semiconductor device, a lower portion electrode
12
comprised of TiN/Al—Si/Ti/TiON/Ti layers is formed on a semiconductor substrate
10
, a dielectric film
14
comprised of a Ta
2
O
5
layer is formed thereon, and an upper portion electrode
16
comprised of a TiN layer is further formed thereon.
On an upper surface of the upper portion electrode
16
, insulator films
18
,
20
comprised of an SiN layer and an SiO
2
layer, respectively, and metal electrode wirings
24
,
26
are formed in via holes
22
formed in the insulator films
18
,
20
, respectively.
In the above-mentioned process for fabricating a semiconductor device, after forming a capacitance element, an insulator film
28
comprised of a spin on glass (hereinafter, frequently referred to simply as “SOG”) is formed and the entire surface of the insulator film
28
is etched to planarize the insulator film.
However, when the insulator film
28
is planarized as mentioned above, a problem occurs in that the capacitance value of the capacitance element is fluctuated or the reliability of the capacitance element is deteriorated.
The reason that such a problem occurs resides in that the portion in which the capacitance element is formed (for example, the portions indicated by characters A and B in
FIG. 5
) has a large protrusion step, as compared to another field region, and therefore, the insulator film in the capacitance element portion is removed in the planarization step, so that the capacitance element suffers a damage or also the upper portion electrode and the dielectric film are etched.
It is an object of the present invention to provide a process for fabricating a semiconductor device, which can prevent the capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability caused in the planarization step.
SUMMARY OF THE INVENTION
For attaining the above object, the present invention provides a process for fabricating a semiconductor device, comprising the steps of: forming, on an insulator formed on a semiconductor substrate, a first wiring layer to be a lower portion electrode for a capacitance element; forming, on the first wiring layer, a dielectric film for forming the capacitance element; forming, on the dielectric film, a second wiring layer to be an upper portion electrode for the capacitance element; and removing the dielectric film and the second wiring layer other than a region in which a capacitance is to be formed while removing an unnecessary region of the first wiring layer, wherein after the removing step, the process has a planarization step in which an insulator film is deposited on a surface of the semiconductor substrate and the entire surface of the insulator film is etched or polished to planarize the surface of the substrate, wherein a protective insulator film which is not removed in the planarization step is formed on at least an upper surface of the capacitance element so that the capacitance element is not exposed in the planarization step.
In the process for fabricating a semiconductor device of the present invention, in the first wiring layer formation step, a first wiring layer to be a lower portion electrode for a capacitance element is formed on an insulator formed on a semiconductor substrate.
Then, in the dielectric film formation step, a dielectric film for forming the capacitance element is formed on the first wiring layer, and in the second wiring layer formation step, a second wiring layer to be an upper portion electrode for the capacitance element is formed on the dielectric film.
Then, in the removing step, the dielectric film and the second wiring layer other than a region in which a capacitance is to be formed are removed while removing an unnecessary region of the first wiring layer. Further, in the planarization step, an insulator film is deposited on a surface of the semiconductor substrate and the entire surface of the insulator film is etched to planarize the surface of the substrate.
Prior to the planarization step, a protective insulator film which is not removed in the planarization step is formed on at least an upper surface of the capacitance element so that the capacitance element is not exposed in the planarization step.
By the process having the above characteristic feature, the dielectric film and electrodes constituting the capacitance element are protected from the etching in the planarization step, thus making it possible to prevent the capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability.
As mentioned above, in the process for fabricating a semiconductor device of the present invention, in the formation of a capacitance element on a semiconductor substrate, prior to the planarization step in which the surface of the substrate is planarized after forming the capacitance element, a protective insulator film which is not removed in the planarization step is formed on at least an upper surface of the capacitance element so that the capacitance element is not exposed in the planarization step. Therefore, the upper portion electrode and the dielectric film constituting the capacitance element are not etched and suffer no damage in the planarization processing, so that a capacitance element free from fluctuation in the properties and having high reliability can be obtained.
REFERENCES:
patent: 5234854 (1993-08-01), An et al.
patent: 5461010 (1995-10-01), Chen et al.
patent: 5817555 (1998-10-01), Cho
patent: 5904521 (1999-05-01), Jeng et al.
patent: 5956587 (1999-09-01), Chen et al.
patent: 6274435 (2001-08-01), Chen
Chen Kin-Chan
Depke Robert J.
Holland & Knight LLC
Sony Corporation
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