Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2007-03-09
2010-11-23
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S357000, C257SE21608
Reexamination Certificate
active
07838374
ABSTRACT:
The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type. Thereafter a second semiconductor region (8) of the first conductivity type, comprising, for example, an emitter region, is formed on a part of the base region (7). This method provides for the formation of a bipolar transistor with an advantageous decrease of the extrinsic collector to base region (6,7) capacitance by the fact that the value of this capacitance is mainly determined by the buried isolation region (15) which has a substantially lower dielectric constant than that of the collector to base region (6,7) junction.
REFERENCES:
patent: 5439832 (1995-08-01), Nakamura
patent: 5620907 (1997-04-01), Jalali-Farahani et al.
patent: 6395608 (2002-05-01), Shin et al.
patent: 2001/0028093 (2001-10-01), Yamazaki et al.
patent: 2004/0188797 (2004-09-01), Khater et al.
patent: 2004/0224461 (2004-11-01), Dunn et al.
patent: 2004/0262715 (2004-12-01), Miura et al.
patent: 0818829 (1998-01-01), None
patent: 1096557 (2001-05-01), None
patent: 2805924 (2001-09-01), None
Kyoung Hwan Yeo et al; “A Partially Insulated Field-Effect Transistor (PIFET) As a Candidate for Scaled Transistors”. IEEE Electron Device Letters, IEEE, Piscataway, NJ, USA. vol. 25, No. 6, Jun. 2004, pp. 387-389.
Yongsik Jeong et al; “FMAX Enhancement in INP-Based DHBTS Using a New Lateral Reverse-Etching Technique”. 2003 International Conference Indium Phosphide and Related Materials. Conference Proceedings. (IPRM). Santa Barbara, CA, May 12-16, 2003, International Conference on Indium Phosphide and Related Materials, New York, NY. IEEE, US, May 12, 2003. pp. 22-25.
Piontek Andreas M.
Van Noort Wibo D.
Zonsky Jan
Chaudhari Chandra
NXP B.V.
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