Method of manufacture of stacked gate MOS structure for multiple

Details Method of manufacture of stacked gate MOS structure for multiple Method of manufacture of stacked gate MOS structure for multiple

1998-05-11

2000-07-25

Bowers, Charles

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

H01L 2120

Patent

active

060936169

ABSTRACT:
This method forms a capacitor structure on a semiconductor substrate for providing split voltages for semiconductor circuits by the following steps. Form an active area in the substrate serving as a lower capacitor plate for a bottom capacitor and then form a thin dielectric layer and field oxide regions on the substrate, and cover the dielectric layer with a capacitor plate over the active area to complete the bottom capacitor. Form a thick dielectric layer over the device and a via through the thick dielectric layer to the upper capacitor plate. Form a second lower plate for a top capacitor. Form an inter-layer dielectric layer over the second lower plate. Form an upper capacitor layer over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.

REFERENCES:
patent: 3897282 (1975-07-01), White
patent: 5049979 (1991-09-01), Hashemi et al.
patent: 5266507 (1993-11-01), Wu
patent: 5324676 (1994-06-01), Guterman
patent: 5604367 (1997-02-01), Yang
patent: 5606521 (1997-02-01), Koo et al.
patent: 5644528 (1997-07-01), Kojima

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