Method of manufacture of contact plug and interconnection...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S639000, C257SE21577

Reexamination Certificate

active

07615485

ABSTRACT:
A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

REFERENCES:
patent: 2001/0019142 (2001-09-01), Nakahata et al.
patent: 2002/0098686 (2002-07-01), Kobayashi et al.
patent: 2005/0139904 (2005-06-01), Kamigaichi et al.
patent: 2005/0181542 (2005-08-01), Enquist
patent: 2007/0037379 (2007-02-01), Enquist et al.
patent: 2007/0057316 (2007-03-01), Yaegashi
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patent: 2003-243619 (2003-08-01), None
patent: 2004-6433 (2004-01-01), None
patent: 2004-14783 (2004-01-01), None
patent: 2004-356521 (2004-12-01), None

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