Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2002-07-24
2004-02-24
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
Reexamination Certificate
active
06696352
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of producing of layered wafers with support, sacrificial and device layers. More particularly, the present invention relates to fabrication methods for wafers with a handle silicon wafer, polymeric intermediate layer and thin single crystalline silicon device layer. The handle and the device wafers may contain preformed semiconductor, optoelectronics or microelectromechanical (MEMS) devices.
BACKGROUND OF THE INVENTION
The use of layered initial substrates instead of bulk initial substrates is often advantageous to semiconductor manufacturing. Layered initial substrates are widely used in microelectronics, MEMS, and optoelectronics applications. Microelectronics uses (1) silicon-on-insulator (SOI), (2) silicon-on-sapphire, and (3) epitaxial types of the initial layered substrates. MEMS use SOI, silicon-on-adhesive, polysilicon-on-insulator, silicon-on-glass, and other types of initial layered substrates. The most useful are 3-layer structures with (1) top device layer, (2) middle sacrificial/spacer (for MEMS), or dielectric (for integrated circuits) layer, and (3) bottom support layer.
In previous art there is known a method of making silicon-on-adhesive wafers. According to Wan in U.S. Pat. No. 6,060,336 the device wafer
103
in
FIG. 1
is bonded to a substrate wafer
101
with an organic adhesive layer
102
. The wafer assembly consisting of members
101
,
102
, and
103
undergo for curing of the adhesive
102
. After said curing the assembly consists of device wafer
103
, substrate wafer
101
, and cured adhesive layer
104
. The device wafer
103
is usually thinned by polishing or other means. After the thinning the assembly consists of substrate wafer
101
, cured adhesive
104
, and device layer
105
. The cured adhesive layer
104
serves as support and spacer
107
. The remainder of the organic adhesive layer
109
serves as a sacrificial layer, which is removed by a dry etch means. Said device wafer is patterned
106
,
108
,
110
to form part of a MEMS device. An adhesive layer is very convenient for MEMS manufacturing as a sacrificial layer. It (1) can be made adequately thick or thin, (2) can be etched away with high selectivity to silicon and to silicon dioxide, (3) does not require etchants (such as KOH) that can poison semifinished signal conditioning circuits (CMOS) integrated on the same silicon die with micromechanics, and is (4) highly tolerant to silicon wafer surface roughness and particle contamination.
Disadvantages of Wan's process are as follows:
The minimum achievable thickness of the top single crystalline layer is limited to about 5 to 10 microns with the etchback technique disclosed. Further etchback to get a thinner layer give rise to thickness non-uniformity of the thinned layer and subsequent yield drop for the finished MEMS devices. The minimum achievable thickness also limits a scaling down of the micromechanical part of the MEMS. The scaling down limit, in turn, limits cost, the achievable integration level, and functional capabilities of final MEMS.
The suspended micromechnical members cannot be single-chip integrated with signal conditioning circuitry (CMOS). Single-chip integration means here that interconnections between micromechanical and microelectronic parts are made by deposition and patterning of a conductive layer (aluminum, polysilicon, etc.). Due to Wan, the signal conditioning circuits are made inside the bonded wafer pair and electrically connected to the suspended micromechanics with wires. This multichip structure prevents a batch processing with subsequent limitations on cost, scaling down, applicability to system-on-a-chip concept, etc.
Bubbles in the adhesive layer. Wan teaches to add solvents to the adhesive before applying to adjust the viscosity of the adhesive. The adhesive with the solvent are placed in between two wafers and cured. The solvent does not have a path to escape from the adhesive layer by evaporation and thus unwanted bubbles are formed.
In previous art there is a process for making SOI wafers. According to U.S. Pat. No. 5,374,564 by Bruel schematically illustrated on
FIG. 2
, thin monocrystalline semiconductor material films are prepared, by subjecting a semiconductor material wafer having a planar face
4
to the following process steps: a first step of implantation by bombardment of the face
4
of the said wafer
6
(which might have a thin silicon dioxide layer
10
) by means of ions
2
creating in the volume of said wafer a layer of gaseous microbubbles
3
defining in the volume of said wafer a lower region
1
constituting the mass of the substrate and an upper region
5
constituting the thin film, a second stage of intimately contacting the planar face of said wafer with a stiffener
7
constituted by at least one rigid material layer, a third stage of heat treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment was carried out and sufficient to create by a crystalline rearrangement effect in said wafer and a pressure effect in the said microbubbles, a separation
8
between the thin film and the mass of the substrate. The finished structure of Bruel's process is a silicon-on-insulator (SOI) wafer
7
. MEMS devices can be fabricated on those wafers. SOI substrates fabricated by Bruel's process are very suitable for integrated circuits manufacturing. In some cases, the Bruel's SOI are very suitable for MEMS manufacturing because of thin and high quality top single-crystalline silicon layer.
Disadvantages of the Bruel process include the following:
Thickness of a silicon dioxide layer is too small for many of MEMS applications. The thickness cannot exceed about 1.5 micrometers for conventional silicon dioxide grown or deposited on silicon. The silicon dioxide serves as a sacrificial layer to form spacer for suspended micromechanics. For many micromechanical applications bigger spacers are needed.
It is difficult to integrate suspended micromechanical members with CMOS signal conditioning circuits using a single SOI initial substrate. If the micromechanics is fabricated first, then the suspended parts cannot survive high temperature steps required in subsequent CMOS manufacturing. If the CMOS is fabricated first, then CMOS cannot survive selective etch step (using typically KOH) required in subsequent release process to form MEMS.
Initial SOI substrates are expensive (5 to 10 times more expensive than similar size bulk silicon substrates) thus making difficult an economically profitable manufacturing of the final MEMS.
Silicon dioxide is not a preferred sacrificial layer for many MEMS applications.
The direct wafer bonding step imposes very strict requirements on the wafer surface roughness and particle contamination on the wafer surfaces to be mated. It requires more expensive process equipment with a given process yield level.
In previous art there is known a process Usenko, U.S. Pat. No. 6,352,909 for liftoff of a layer from a substrate. In Usenko process a layer is lifted off from a silicon wafer to further form a silicon-on-insulator (SOI) sandwich structure, wherein a separative interlayer comprises a thin quasi-continuous gaseous layer and said interlayer is obtained by gettering monatomic hydrogen into a preformed buried defect-rich layer preferably created by implantation and evolving of hydrogen-filled getter layer into the quasi-continuous gaseous layer by thermal treatment means.
The Usenko process allows fabricating lower cost SOI as compared with the Bruel process. However, the rest of disadvantages as concerning to further MEMS manufacturing remain.
A combination of Bruel's process giving a thin top silicon layer with the Wan's process giving versatile sacrificial layer would be advantageous to the art. However, the processes cannot be directly combined. Bruel's process requires 500° C. annealing to evolve hydrogen-rich layer into a microbubble layer thus enabling cleavage to release the layer from the substrate
Carr William
Usenko Alexander
Blum David S
Jr. Carl Whitehead
Silicon Wafer Technologies Inc.
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