Method of manufacture for an integrated circuit having a BIST ci

Details Method of manufacture for an integrated circuit having a BIST ci Method of manufacture for an integrated circuit having a BIST ci

1999-04-08

2000-10-24

Chaudhari, Chandra

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

H01L 2348, G01R 3126

Patent

active

06136620&

ABSTRACT:
In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.

REFERENCES:
patent: 4636832 (1987-01-01), Abe et al.
patent: 4984061 (1991-01-01), Matsumoto
patent: 5502337 (1996-03-01), Nozaki
K. Mukai, A. Hiraiwa, S. Muramatsu, I. Yoshida and S. Harada; "A New Integration Technology that Enables Forming Bonding Pads on Active Areas"; IEDM 1981: pp. 62-65.

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