Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2008-06-23
2010-11-16
Chu, Gabriel L (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C709S239000
Reexamination Certificate
active
07836350
ABSTRACT:
Provided is a method of controlling a computer system that includes: a computer; a first storage device connected to the computer via a first path and a second path; and a second storage device externally-connected to the first storage system via a third path and connected to the computer via a fourth path, the first storage device providing a first storage area to the computer, the second storage device including a second storage area corresponding to the first storage area, the method including: judging whether or not a fault has occurred in at least one of the first to fourth paths; selecting, a path used for access to the first or second storage area; and transmitting the access request for the first or second storage area by using the selected path. Accordingly, in the computer system, an application can be prevented from being stopped despite a fault in a path.
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Office Action from Japanese Patent Office for Japanese Patent Application 2008-107852 mailed May 18, 2010.
Gemba Ryu
Haramai Naoki
Kondo Atsushi
Oyama Kazuhiro
Yokouchi Hiroshi
A. Marquez, Esq. Juan Carlos
Chu Gabriel L
Hitachi , Ltd.
Stites & Harbison PLLC
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