Method of making upper conductive line in dual damascene...

Details Method of making upper conductive line in dual damascene... Method of making upper conductive line in dual damascene...

2001-01-05

2003-06-10

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S702000

Reexamination Certificate

active

06576555

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor process, and more specifically, to a dual damascene process for copper interconnection line and via.
BACKGROUND OF THE INVENTION
The technology of fabricating integrated circuits (IC) continuous to advance in the number of transistors, capacitors, or other electronic devices which can be fabricated on a single IC chip. The increase level of integration is being achieved in large part depended on decreasing the minimum feature sizes and on the multi-level connection technology. However, many difficult problems in the multi-level metallization are demanded to improve. The problems are: (1) to deposit a void free inter-level dielectric (ILD) that can fill the small gaps between lines without reliability problem, (2) to provide an efficient damascene process for connecting between multiple wiring levels without misalignment during via hole and trenches patterning.
Recently, in U.S. Pat. No. 6,087,251, Hsu proposed a dual damascene process to solve the issues of complicated processes for an excessive number of IMD deposition steps and misalignment while forming via holes by photolithography and etching. The processes are as follows: firstly, referring to
FIG.1A
, a cross-sectional view showing a semiconductor substrate
200
with first IMD layer
201
thereto connect devices (not shown) is provided. A silicon nitride layer
202
is then formed on the first IMD
201
. Thereafter, the silicon nitride layer
202
is patterned to form trenches
204
a
,
204
b
and
204
c.
As shown in
FIG. 1B
, a conductive layer is then refilled into the trenches. The conductive layer (not shown) over the level surface of the nitride layer
202
is removed to form conductive lines
206
a
,
206
b
, and
206
c
by CMP (chemical/mechanical polish) process. Referring to
FIG. 1C
, after a photoresist pattern
208
shields the conductive line
206
b
, an etch-back process is then done to remove away an upper portion of conductive lines
206
a
,
206
c
. The etch level comes up to leave about a predetermined thickness in the trenches so as to form lower conductive lines in trenches
206
a
′ and
206
c
′ and a via
206
b.
Referring to
FIG. 1D
, refilling the trenches
206
a
′ and
206
c
′ with the nitride layer and using CMP to remove the excess nitride layer over surface level of the conducive line
206
b
are successively performed. After that an oxide layer
210
serves as a second IMD layer formed on the nitride layer
202
is followed.
Referring to
FIG. 1E
, the oxide layer
210
is then patterned to form horizontal trenches
212
until a surface of the via
206
b
is exposed. The trenches are then refilled with conductive layer. The metal removal over the oxide layer
210
by CMP is followed so as to upper conductive lines.
The aforementioned prior art defines the via and the trenches simultaneously without the step of defining the via hole and thus can solve the misalignment caused by the definition the via hole. In the case of copper as material of the lower conductive lines and the via some of the problems are necessary to overcome. For instance, the exposed surface of the copper via
206
b
is usually formed with a thin copper oxide layer. A plasma bombardment is necessary to be done to remove it. However, the copper-redeposit on the sidewall of the trenches
212
during sputtering the copper oxide on the via will degrade the quality of the oxide layer.
Hence, the motivation of the present invention-is to solve the problems of the contamination by copper redeposit.
SUMMARY OF THE INVENTION
An object of the present invention is to solver the problem of copper redeposit on the sidewall of the trenches when lower conductive lines are made of copper.
A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The method comprises following steps: first, a substrate having nitride layer is provided. The nitride is then patterned to form a plurality of first trenches therein. A copper layer is then refilled in the trenches. After a CMP process to remove a portion of the copper layer over a level of surface of the nitride layer so as to form a plurality of conductive lines, a mask pattern is then shielded one conductive line which is served as a via. Thereafter, each upper portion of the conductive lines are etched away until a predetermined thickness except the via which has a mask pattern to prevent from etch. After the mask pattern is removed, the trenches formed resulting from conductive line etching is then filled with a nitride layer. A CMP process is then followed to remove the excess nitride layer over a level of surface of the via,
An oxide layer on the nitride layer is then formed and patterned to form trenches. A barrier layer is then deposited on the resulting exposed surface. An anisotropic etching process is then carried out to form barrier spacers on the sidewall of the trenches. Subsequently, an inert gas bombardment is done to remove a copper oxide layer so as to clean a surface of the via. Next, a conductive layer refilled in the trenches followed by a CMP process are successively performed to form a plurality of upper conductive lines.


REFERENCES:
patent: 6211063 (2001-04-01), Liu et al.
patent: 6215189 (2001-04-01), Toyoda et al.
patent: 6323118 (2001-11-01), Shih et al.
patent: 6384480 (2002-05-01), McTeer

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