Method of making total dielectric semiconductor device isolation

Details Method of making total dielectric semiconductor device isolation Method of making total dielectric semiconductor device isolation

1997-10-08

1999-08-03

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

438426, H01L 21762

Patent

active

059337451

ABSTRACT:
A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

REFERENCES:
patent: 5039621 (1991-08-01), Pollack
patent: 5561076 (1996-10-01), Yoshino

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