Method of making tall flip chip bumps

Details Method of making tall flip chip bumps Method of making tall flip chip bumps

2001-10-12

2004-06-29

Huff, Mark F (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S315000, C430S322000, C430S324000, C438S612000, C228S180210, C228S180220

Reexamination Certificate

active

06756184

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a process of forming a bump on a substrate.
BACKGROUND OF THE INVENTION
A flip chip microelectronic assembly includes a direct electrical connection of face down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with a wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. Flip chips are also known as “direct chip attach” because the chip is directly attached to the substrate, board, or carrier by the conductive bumps.
The use a flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services. In some cases, the elimination of old technology packages and bond wires may reduce the substrate or board area needed to secure the device by up to 25 percent, and may require far less height. Further, the weight of the flip chip can be less than 5 percent of the old technology package devices.
Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in the high speed off-chip interconnection.
Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips can be stacked in 3-D geometries over other flip chips or other components.
Flip chips also provided the most rugged mechanical interconnection. Flip chips when underfilled with an adhesive such as an epoxy, can withstand the most rugged durability testing. In addition to providing the most rugged mechanical interconnection, flip chips can be the lowest cost interconnection for high-volume automated production.
The bumps of the flip chip assembly serve several functions. The bumps provided an electrical conductive path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provided part of the mechanical mounting of the chip to the substrate. A spacer is provided by the bumps that prevents electrical contact between the chip and the substrate connectors. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
Flip chips are typically made by a process including placing solder bumps on a silicon wafer. The solder bump flip chip processing typically includes four sequential steps: 1) preparing the wafer for solder bumping; 2) forming or placing the solder bumps on the wafer; 3) attaching the solder bumped die to a board, substrate or carrier; and 4) completing the assembly with an adhesive underfill. A brief description of the prior art methods of performing the first step will provide a better background for understanding the present invention.
The first step in a typical solder bumping process involves preparing the semiconductor wafer bumping sites on bond pads of the individual integrated circuits defined in the semiconductor wafer. The preparation may include cleaning, removing insulating oxides, and preparing a pad metallurgy that will protect the integrated circuits while making good mechanical and electrical contact with the solder bump. Accordingly, protective metallurgy layers may be provided over the bond pad. Ball limiting metallurgy (BLM) or under bump metallurgy (UBM) generally consists of successive layers of metal. The “adhesion” layer must adhere well to both the bond pad metal and the surrounding passivation, provide a strong, low-stress mechanical and electrical connection. The “diffusion barrier” layer prevents the diffusion of solder into the underlying material. The “solder wettable” layer provides a wettable surface for the molten solder during the solder bumping process, for good bonding of the solder to the underlying metal.
In fabrication of a flip-chip bond structure, the fabrication process requires a tight control of interface processes and manufacturing parameters in order to meet very small dimensional tolerances. Various techniques may be utilized to fabricate a UBM structure and to deposit the solder bump. A few widely used methods of depositing bumps include evaporation, electroplating, electroless plating and screen-printing. Kung et al, U.S. Pat. No. 6,179,200 provides a description of these more widely used methods of depositing bumps as follows.
The formation of solder bumps can be carried out by an evaporation method of Pb and Sn through a mask for producing the desired solder bumps. When a metal mask is used, UBM metals and solder materials can be evaporated through designated openings in the metal mask and be deposited as an array of pads onto the chip surface.
In the evaporation method, a wafer is first passivated with an insulating layer, via holes are then etched through the wafer passivation layer which is normally SiO
2
to provide a communication path between the chip and the outside circuit. After a molybdenum mask is aligned on the wafer, a direct current sputtering cleans the via openings formed in the passivation layer and removes undesirable oxides. A cleaned via opening assures low contact resistance and good adhesion to the SiO
2
. A chromium layer is evaporated through a metal mask to form an array of round metal pads each covering an individual via to provide adhesion to the passivation layer and to form a solder reaction barrier to the aluminum pad underneath. A second layer of chromium/copper is then co-evaporated to provide resistance to multiple reflows. This is followed by a final UBM layer of pure copper which forms the solderable metallurgy. A thin layer of gold may optionally be evaporated to provide an oxidation protection layer. These metal-layered pads define the solder wettable regions on the chips, which are commonly referred to as the ball limiting metallurgy (BLM) or under bump metallurgy (UBM). After the completion of UBM, solder evaporation occurs through a metal mask, which has a hole diameter slightly greater than the UBM mask-hole diameter. This provides the necessary volume for forming a subsequent solder ball. A solder reflow process is performed at a temperature of about 350 degrees Celsius to melt and homogenize the evaporated metal pad and to impart a truncated spherical shape to the solder bump. The evaporation method, even though well established and has been practiced for a long time in the industry, is a slow process and thus can not be run at a high throughput rate.
A second method for forming solder bumps is the electroplating method. In an electroplating process, UBM layers are first deposited, followed by the deposition of a photoresist layer, the patterning of the photoresist layer, and then the electro-deposition of a solder material into the photoresist openings. After the electro-deposition process is completed, the photoresist layer can be removed and the UBM layers can be etched by using the plated solder bumps as a mask. The solder bumps are then reflowed in a furnace reflow process. The photolithography/electroplating technique is a simpler technique than evaporation and is less expensive because only a single masking operation is required. However, electroplating requires the deposition of a thick and uniform solder

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