Method of making stacked-capacitor for a dram cell same

Details Method of making stacked-capacitor for a dram cell same Method of making stacked-capacitor for a dram cell same

1991-12-10

1993-08-17

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, H01L 2170

Patent

active

052368599

ABSTRACT:
There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

REFERENCES:
patent: 5049957 (1991-09-01), Inoue et al.
patent: 5068698 (1991-11-01), Koyama et al.
patent: 5071781 (1991-12-01), Seo et al.
S. Inoue, "A New Stacked Capacitor Cell with Trim Box Structured Storage Node," 21st Comf. Oda Solid State Devices and Materials Tokyo, 1989 pp. 141-144.

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