Method of making SRAM cell having single layer polysilicon thin

Details Method of making SRAM cell having single layer polysilicon thin Method of making SRAM cell having single layer polysilicon thin

1997-07-16

1999-05-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438385, 438649, H01L21/8244

Patent

active

059045124

ABSTRACT:
A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors. This arrangement results in a TFT SRAM cell that can be implemented using simple fabrication techniques, such as single poly logic processes or ASIC processes.

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Yamanaka et al., "Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography", IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995.

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