Method of making SOI circuit for higher temperature and higher v

Details Method of making SOI circuit for higher temperature and higher v Method of making SOI circuit for higher temperature and higher v

1996-06-28

1999-04-13

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438164, 438154, 438228, H01L 2100

Patent

active

058937293

ABSTRACT:
Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

REFERENCES:
patent: 4232327 (1980-11-01), Hsu
patent: 5024965 (1991-06-01), Chang et al.
patent: 5306656 (1994-04-01), Williams et al.
patent: 5416043 (1995-05-01), Burgener et al.
patent: 5426062 (1995-06-01), Hwang
patent: 5440161 (1995-08-01), Iwamatsu et al.

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