Method of making semiconductor-on-insulator device with closed-g

Details Method of making semiconductor-on-insulator device with closed-g Method of making semiconductor-on-insulator device with closed-g

1996-04-01

1997-11-04

Niebling, John

Fishing, trapping, and vermin destroying

437 41, 257347, 257350, 257355, H01L 21265, H01L 2184

Patent

active

056839189

ABSTRACT:
A body-tied MOSFET (14) is used in a protection circuit (10) of an SOI device (20) where the MOSFET's drain regions (38) lie outside MOSFET's closed-gate electrode (34). Electrical characteristics of the body-tied MOSFET (14) can be changed by varying the ratio of the total source region area to the total body-tied region area (tie frequency). The total electrical device width is the sum of the individual source region (36) widths. More charge can be placed on the drain region (38) compared to a drain region on the inside because the interfacial area between the drain region and channel region is larger. The device (20) can be formed without having to develop new processing steps or use marginal processing steps. Body ties to an underlying substrate are unnecessary.

REFERENCES:
patent: 4063274 (1977-12-01), Dingwall
patent: 4173022 (1979-10-01), Dingwall
patent: 4272881 (1981-06-01), Angle
patent: 4274193 (1981-06-01), Angle
patent: 4423431 (1983-12-01), Sasaki
patent: 4965213 (1990-10-01), Blake
patent: 4989057 (1991-01-01), Lu
patent: 5372959 (1994-12-01), Chan
patent: 5374573 (1994-12-01), Cooper et al.
patent: 5399507 (1995-03-01), Sun
patent: 5567968 (1996-10-01), Tsuruta et al.
patent: 5578513 (1996-11-01), Maegawa
patent: 5580802 (1996-12-01), Mayer et al.
patent: 5616935 (1997-04-01), Koyama et al.
Colinge; Silicon-on-Insulator Technology: Materials to VLSI; Kluwer Academic Publishers; pp. 102-106 (1991), month unknown.
Wolf; Silicon Processing For The VLSI ERA vol. 2: Process Integration; Lattice Press; pp. 72-75 (1990), month unknown.
Palumbo, et al.; "Design and Characterication Of Input Protection Networks For CMOS/SOS Applications;" EOS/ESD Symposium Proceedings; pp. 182-187 (Sep. 1986).

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