Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
1999-09-30
2001-04-24
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S297000, C438S225000, C257S347000, C257S335000
Reexamination Certificate
active
06221737
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is in the field of Semiconductor devices, and relates more specifically to a method of making devices such as MOSFETS and diodes, including SOI devices, suitable for high-voltage and power applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, conduction losses and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as conduction losses. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
Improvements over a basic structure, in which increased breakdown voltages are achieved by providing a linear doping profile in the drift region, are shown in related U.S. Pat. No. 5,246,870 and U.S. Pat. No. 5,412,241, both commonly assigned with the instant application and incorporated herein by reference. In these SOI devices, the drift region between the channel and drain in a lateral MOS structure is provided with various features, such as a thinned portion and a linear lateral doping density profile, which result in substantially increased breakdown voltage characteristics. Additionally, a top field plate is provided over a field oxide of essentially constant thickness to permit twice the conducting charge to be placed in the drift region, thereby reducing conduction losses without reducing breakdown voltage. However, to maintain high breakdown voltage, the total amount of conduction charge near the source side of the drift region must be kept very small, thereby leading to a bottleneck for current flow and preventing optimum reduction in conduction losses.
Another improvement over the basic SOI structure is shown in U.S. Pat. No. 5,648,671, also commonly assigned with the instant application and incorporated herein by reference. This patent shows a lateral thin-film SOI device with a linearly-graded field oxide region and a linear doping profile, features which serve to reduce conduction losses without reducing breakdown voltage. Yet another improved high-voltage thin-film device is disclosed in U.S. patent application Ser. No. 08/998,048, commonly assigned with the instant application, co-invented by the present inventors and incorporated herein by reference. This application discloses another technique for improving such devices, employing a step oxide region of intermediate thickness to increase current-carrying capability while maintaining a high breakdown voltage.
While all of the foregoing structures offer an improvement over standard SOI structures, they still suffer from the drawback that they cannot operate effectively and efficiently at high current levels in the source-follower mode, wherein a “source-high” bias condition may be encountered during operation and a high breakdown voltage must be maintained in a device which must also handle high current levels.
A lateral thin-film SOI device configuration of the type described above, but in which operation, and particularly operation of a MOSFET device in the source-follower mode, is enhanced by significantly increasing permissible saturated current flow and reducing the on resistance of the device structure while maintaining high breakdown voltage capability, is described in allowed U.S. patent application Ser. No. 09/100,832, filed Jun. 19, 1998 by the present inventors, commonly assigned with the instant application, and incorporated herein by reference in its entirety. The advantages of the foregoing structures are achieved by providing the disclosed structures with both a graded top oxide and a graded drift region. While devices of this type can be made using conventional prior-art doping and LOCOS techniques, as noted in Applicants' earlier application, such prior-art techniques are relatively complex, expensive and time consuming.
Accordingly, it would be desirable to have a method of making semiconductor devices with a graded top oxide and a graded drift region using a relatively simple, economical and rapid fabrication process.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of making a semiconductor device, such as a MOSFET or a power diode, capable of improved performance, by virtue of a design configuration which results in a significant increase in the saturated current flow and a reduction in the minimum attainable specific on resistance of the device structure without compromising the breakdown voltage capability of the device.
It is a further object of the invention to provide a method of making a semiconductor device with a graded top oxide and a graded drift (or other underlying semiconductor) region in order to achieve improve performance, with the method being simpler, more economical and more rapid than presently-known methods.
In accordance with the invention, these objects are achieved, for example, in a semiconductor device of the type having a semiconductor substrate, a thin buried oxide insulating layer on the substrate, and a lateral semiconductor device provided in a thin semiconductor film on the thin buried oxide. The thin semiconductor film includes a first region of a first conductivity type, a second region of a second conductivity type opposite to that of the first and spaced apart from the first region by a lateral drift region of the second conductivity type, a top oxide insulating layer over the thin semiconductor film, and a conductive field plate on the top oxide insulating layer. In accordance with the invention, the objects discussed above are achieved by a method of providing the top oxide insulating layer with a layer portion adjacent the first region which increases in thickness in a substantially continuous manner in a direction from the first region toward the second region over a distance of at least about a factor of five greater than a maximum thickness of the top oxide insulating layer, and by providing the lateral drift region with a region portion adjacent the first region which decreases in thickness in the same substantially continuous manner in a direction from the first region toward the second region and over the same distance. Such a configuration provides a substantially thicker semiconductor film region adjacent the first region and also provides a substantially thinner top oxide insulating layer in this region. Additionally, such a device configuration avoids sharp edges and steep slopes in the oxide and semiconductor film layers in this region. These features, in combination, result in the performance advantages discussed above, which are of particular importance in source-follower mode operation of MOSFET devices.
In accordance with the invention, the foregoing features are achieved by a method including the steps of forming an oxidation mask including silicon nitride on the thin semiconductor film and then patterning a portion of the oxidation mask with a series of sequential openings of different widths, a portion of the openings having a width less than the maximum thickness of the top oxide insulation layer. The thin semiconductor film is then oxidized using the oxidation mask to grow the top oxide insulation layer and lateral drift region portions which change in thickness.
In a preferred embodiment of the invention, the method is used to fabricate a MOSFET device, while in a further preferred embodiment of the invention the method is used to fabricate a diode, in which case the devices made in accordance with the method of the invention will provide enhanced performance due to a reduced forward voltage drop at a given current (thus reducing conduction losses) and can also increase diode breakdown voltage.
In further preferred embodiments of the invention, the increases and decreases in thickness described above may occur in either a substantially linear manner, or in a nonlinear manner such as in accordance with a square-root function.
In yet a further preferred embodiment of the invention onl
Letavic Theodore
Simpson Mark
Biren Steven R.
Blum David S
Bowers Charles
Philips Electronics North America Corporation
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