Method of making p-channel and n-channel MIS transistors...

Details Method of making p-channel and n-channel MIS transistors... Method of making p-channel and n-channel MIS transistors...

2008-09-10

2010-06-29

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S199000, C438S198000

Reexamination Certificate

active

07745888

ABSTRACT:
A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

REFERENCES:
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patent: 2006/0145201 (2006-07-01), Shiga
patent: 2006/0197157 (2006-09-01), Koyama et al.
patent: 2007/0048919 (2007-03-01), Adetutu et al.
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patent: 2008/0258230 (2008-10-01), Koyama et al.
patent: WO 2004009515 (2004-01-01), None
Schaeffer, J. K. et al., “Challenges for the Integration of Metal Gate Electrodes,” IEEE, 2004 IEDM, pp. 287-290, (2004).

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