Method of making MIS field effect transistor having a lightly-do

Details Method of making MIS field effect transistor having a lightly-do Method of making MIS field effect transistor having a lightly-do

1985-02-21

1986-07-01

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29576B, 29580, 148187, 156651, 156653, 156657, 156662, 357 41, 357 91, H01L 21306, H01L 2122, B44C 122, C03C 1500

Patent

active

045978271

ABSTRACT:
An LDD MIS structure without a lightly-doped source region can be formed by the use of the conventional self-alignment technique. The structure includes in a silicon substrate a gate region, a heavily-doped drain region, a heavily-doped source region, and a lightly doped drain region. The gate region consists of a gate electrode and a side-wall spacer. The lightly-doped drain region is formed under the side-wall spacer, and in the silicon substrate.

REFERENCES:
patent: 4442589 (1984-04-01), Doo et al.
patent: 4455738 (1984-06-01), Houston et al.
patent: 4478679 (1984-10-01), Chang et al.
IEDM-82, 1982, A Half Micron Mosfet Using Double Implanted LDD, Seiki Ogura et al., pp. 718-721.

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