Method of making memory chips using memory tester providing fast

Semiconductor device manufacturing: process – Repair or restoration

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365200, 371 103, H01L 2100, G11C 700, G11C 2900

Patent

active

057957975

ABSTRACT:
A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified. In cases where multiple structures have the same highest priority, alternative criteria are used to select a single element for replacement. Preprocessing is used to focus, at each iteration, on the best faulty elements to replace. One preprocessing technique is to constrain the choice for replacement to faulty cells within certain clusters, which, based on the distribution of failures will require either a row or column for repair. Another preprocessing technique is to constrain the choice for replacement to faulty cells within a segment which must use either a row or column for repair. When the choice for replacement in a group of faulty cells is constrained to faulty cells which require a redundant row or column for repair, only the priorities of the rows or columns, respectively, in that group of cells is considered.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4627053 (1986-12-01), Yamaki et al.
patent: 4628509 (1986-12-01), Kawaguchi
patent: 4639915 (1987-01-01), Bosse
patent: 4736373 (1988-04-01), Schmidt
patent: 4876685 (1989-10-01), Rich
patent: 5363382 (1994-11-01), Tsukakoshi
patent: 5514628 (1996-05-01), Enomoto et al.
Tar et al. Defect Analysis System Speeds Test And Repair Of Redundant Memories, Electronics International, vol. 57 (1984) Jan., No. 1 pp. 175-179.
Wey et al., On The Repair Of Redundant RAM's IEEE Transactions On Computer-Aided Design, vol. CAD-6, No., 2, Mar. 1997.
Huang et al. Minimizing The Cost Of Repairing WSI Memories Integration, the VLSI Journal (1991) Jun., No. 3.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making memory chips using memory tester providing fast does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making memory chips using memory tester providing fast, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making memory chips using memory tester providing fast will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1114186

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.